Driver, display apparatus including the same and electronic apparatus including the same

Patent metadata

Field	Value
Publication number	US-2026018109-A1
Application number	US-202519097747-A
Country	US
Kind code	A1
Filing date	Apr 1, 2025
Priority date	Jul 11, 2024
Publication date	Jan 15, 2026
Grant date	—

Abstract

A driver includes a first transistor including a control electrode for receiving a clock signal, a first electrode for receiving an input signal, and a second electrode connected to a first node, a second transistor including a control electrode connected to the first node, a first electrode for receiving a first power voltage, and a second electrode connected to a second node, a third transistor for receiving a second power voltage, and connected to the first node and to a third node, a fourth transistor connected to the first and second nodes, a fifth transistor connected to the second node, for receiving the high power voltage, and connected to an output node, and a sixth transistor connected to the third and output nodes, and for receiving the low power voltage, the fourth transistor being an NMOS transistor, and a gate-source voltage of the fourth transistor being less than zero.

First claim

What is claimed is:

1 . A driver comprising:
a first transistor comprising a control electrode configured to receive a clock signal, a first electrode configured to receive an input signal, and a second electrode connected to a first node; a second transistor comprising a control electrode connected to the first node, a first electrode configured to receive a first voltage, and a second electrode connected to a second node; a third transistor comprising a control electrode configured to receive a second voltage, a first electrode connected to the first node, and a second electrode connected to a third node; a fourth transistor comprising an NMOS transistor comprising a control electrode connected to the first node, and a first electrode connected to the second node, and configured to have a gate-source voltage that is less than zero; a fifth transistor comprising a control electrode connected to the second node, a first electrode configured to receive the first voltage, and a second electrode connected to an output node; and a sixth transistor comprising a control electrode connected to the third node, a first electrode connected to the output node, and a second electrode configured to receive the second voltage.

2 . The driver of claim 1 , further comprising a first capacitor comprising a first electrode connected to the third node, and a second electrode connected to the output node.

3 . The driver of claim 1 , further comprising a second capacitor comprising a first electrode configured to receive the first voltage, and a second electrode connected to the second node, wherein the first voltage comprises a high power voltage.

4 . The driver of claim 1 , wherein the first transistor, the second transistor, the third transistor, the fifth transistor, and the sixth transistor comprise PMOS transistors.

5 . The driver of claim 1 , wherein the fourth transistor further comprises a second control electrode connected to the control electrode of the fourth transistor.

6 . The driver of claim 1 , wherein the fourth transistor further comprises a second electrode configured to receive a third voltage,
wherein the second voltage comprises a low power voltage, and wherein the third voltage comprises another low power voltage that is different from the second voltage.

7 . The driver of claim 6 , wherein the third voltage is greater than the second voltage.

8 . The driver of claim 1 , further comprising an eighth transistor comprising a control electrode connected to the third node, and a first electrode connected to the first node,
wherein the fourth transistor further comprises a second electrode configured to receive the second voltage.

9 . The driver of claim 8 , wherein the eighth transistor further comprises a second electrode configured to receive a fourth voltage,
wherein the second voltage comprises a low power voltage, and wherein the fourth voltage comprises another low power voltage that is different from the second voltage.

10 . The driver of claim 9 , wherein the fourth voltage is less than the second voltage.

11 . The driver of claim 8 , wherein the eighth transistor further comprises a second electrode connected to the third node.

12 . The driver of claim 1 , further comprising an eighth transistor comprising a control electrode connected to the third node, and a first electrode connected to the first node,
wherein the fourth transistor further comprises a second electrode configured to receive a third voltage comprising a low power voltage that is different from the second voltage.

13 . The driver of claim 12 , wherein the eighth transistor further comprises a second electrode configured to receive a fourth voltage comprising another low power voltage that is different from the second voltage.

14 . The driver of claim 13 , wherein the third voltage is greater than the second voltage, and
wherein the fourth voltage is less than the second voltage.

15 . The driver of claim 12 , wherein the eighth transistor further comprises a second electrode connected to the third node.

16 . The driver of claim 1 , wherein the first transistor further comprises a second control electrode connected to the control electrode of the first transistor,
wherein the second transistor further comprises a second control electrode connected to the control electrode of the second transistor, wherein the third transistor further comprises a second control electrode connected to the control electrode of the third transistor, wherein the fifth transistor further comprises a second control electrode connected to the control electrode of the fifth transistor, and wherein the sixth transistor further comprise a second control electrode connected to the control electrode of the sixth transistor.

17 . The driver of claim 1 , further comprising a seventh transistor comprising a control electrode configured to receive a reset signal, a first electrode connected to the second node, and a second electrode connected to a second electrode of the fourth transistor.

18 . The driver of claim 1 , further comprising a seventh transistor comprising a control electrode configured to receive a reset signal, a first electrode configured to receive the first voltage, and a second electrode connected to the first node.

19 . A display apparatus, comprising:
a display panel comprising a pixel; a gate driver configured to output a gate signal to the pixel; a data driver configured to output a data voltage to the pixel; and an emission driver configured to output an emission signal to the pixel, wherein the gate driver or the emission driver comprises at least one stage comprising:
a first transistor comprising a control electrode configured to receive a clock signal, a first electrode configured to receive an input signal, and a second electrode connected to a first node;
a second transistor comprising a control electrode connected to the first node, a first electrode configured to receive a first voltage, and a second electrode connected to a second node;
a third transistor comprising a control electrode configured to receive a second voltage, a first electrode connected to the first node, and a second electrode connected to a third node;
a fourth transistor comprising an NMOS transistor comprising a control electrode connected to the first node, and a first electrode connected to the second node, and configured to have a gate-source voltage that is less than zero;
a fifth transistor comprising a control electrode connected to the second node, a first electrode configured to receive the first voltage, and a second electrode connected to an output node; and
a sixth transistor comprising a control electrode connected to the third node, a first electrode connected to the output node, and a second electrode configured to receive the second voltage.

20 . An electronic apparatus, comprising:
a display panel comprising a pixel; a gate driver configured to output a gate signal to the pixel; a data driver configured to output a data voltage to the pixel; an emission driver configured to output an emission signal to the pixel; a driving controller configured to control the gate driver, the data driver, and the emission driver; and a processor configured to output image data and a control signal to the driving controller, wherein the gate driver or the emission driver comprises at least one stage comprising:
a first transistor comprising a control electrode configured to receive a clock si

Assignees

• Samsung Display Co Ltd

Inventors

• Kim Kyung-Hoon
• Kim Yongchan
• Chun Jooyoung

Classifications

• G09G2300/0861

  with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes · CPC title

• G09G2310/0286

  Details of a shift registers arranged for use in a driving circuit · CPC title

• G09G2310/0267

  Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays · CPC title

• G09G2310/08

  Details of timing specific for flat panels, other than clock recovery · CPC title

• G09G2300/0426

  Layout of electrodes and connections · CPC title