Display panel

Patent metadata

Field	Value
Publication number	US-2026013385-A1
Application number	US-202519330298-A
Country	US
Kind code	A1
Filing date	Sep 16, 2025
Priority date	Nov 30, 2018
Publication date	Jan 8, 2026
Grant date	—

Abstract

A display panel may include a substrate, pixels, dummy pixels, and voltage lines. The substrate may include a first transmission region for light transmission and/or sound transmission, a non-display area surrounding the first transmission region, and a display area surrounding the non-display area. The pixels may be arranged on the display area and may emit light. The dummy pixels may be arranged on the non-display area, may include a first dummy pixel, and may emit no light. The voltage lines may transmit voltages to the pixels and the dummy pixels. The voltage lines may include a first voltage line and a second voltage line. The first voltage line may be spaced from the second voltage line, may be aligned with the second voltage line, and may overlap the first dummy pixel. The first transmission region may be positioned between the first voltage line and the second voltage line.

First claim

What is claimed is;:

1 . A display panel comprising:
a substrate including a first transmission region, a second transmission region, a non-display area that surrounds the first transmission region and the second transmission region, and a display area that surrounds the non-display area; emitting pixels arranged on the display area, and configured to emit light; dummy pixels arranged on the non-display area, and configured to emit no light; and driving voltage lines configured to transmit driving voltages to the emitting pixels and the dummy pixels,
wherein the first transmission region and the second transmission region are disposed along a first direction, and
wherein a width of the non-display area in a second direction across the first direction, between the first transmission region and the second transmission region, is smaller than a width of the first transmission region in the second direction.

2 . The display panel of claim 1 , wherein some of the driving voltage lines are separated from each other by the first transmission region or the second transmission region being interposed therebetween.

3 . The display panel of claim 1 . wherein the driving voltage lines include a first driving voltage line, a second driving voltage line, and a third driving voltage line,
wherein the first driving voltage line is spaced from the second driving voltage line and is aligned with the second driving voltage line, wherein the first transmission region is positioned between the first driving voltage line and the second driving voltage line, and
wherein the third driving voltage line intersects a boundary of the non-display area twice and is longer than each of the first driving voltage line and the second driving voltage

4 . The display panel of claim 1 wherein the dummy pixels are disposed between the first transmission region and the second transmission region.

5 . The display panel of claim 1 , wherein the dummy pixels surround the first transmission region and the second transmission region.

6 . The display panel of claim 1 , wherein a width of the second transmission region is different from a width of the first transmission region.

7 . The display panel of claim 6 ,
wherein the width of the non-display area in a second direction across the first direction, between the first transmission region and the second transmission region, is smaller than a width of the second transmission region in the second direction.

8 . The display panel of claim 1 , wherein each of emitting pixels comprises a pixel circuit and a display element, the pixel circuit comprising at least one transistor, the display element being electrically connected to the pixel circuit,
wherein each of dummy pixels comprises a dummy pixel circuit comprising at least one dummy transistor, and wherein a structure of the pixel circuit is same as a structure of the dummy pixel circuit.

9 . The display panel of claim 7 , further comprising a pixel defining layer arranged on the pixel circuit and the dummy pixel circuit,
wherein the pixel defining layer comprises an opening corresponding to each of emitting pixels, and wherein the pixel defining layer has a flat surface overlapping the dummy pixels.

10 . The display panel of claim 1 , further comprising electrode voltage lines intersecting the driving voltage lines and electrically connected to the driving voltage lines via contact holes to form a conductive mesh structure.

11 . A display device comprising:
a substrate including a first transmission region, a second transmission region, a non-display area that surrounds the first transmission region and the second transmission region, and a display area that surrounds the non-display area; an electronic element under the first transmission region of the substrate; emitting pixels arranged on the display area, and configured to emit light; dummy pixels arranged on the non-display area, and configured to emit no light; and driving voltage lines configured to transmit driving voltages to the emitting pixels and the dummy pixels,
wherein the first transmission region and the second transmission region are disposed along a first direction, and
wherein a width of the non-display area in a second direction across the first direction, between the first transmission region and the second transmission region, is smaller than a width of the first transmission region in the second direction.

12 . The display device of claim 11 , wherein some of the driving voltage lines are separated from each other by the first transmission region or the second transmission region being interposed therebetween.

13 . The display device of claim 11 , wherein the driving voltage lines include a first driving voltage line, a second driving voltage line, and a third driving voltage line,
wherein the first driving voltage line is spaced from the second driving voltage line and is aligned with the second driving voltage line, wherein the first transmission region is positioned between the first driving voltage line and the second driving voltage line, and
wherein the third driving voltage line intersects a boundary of the non-display area twice and is longer than each of the first driving voltage line and the second driving voltage

14 . The display device of claim 11 wherein the dummy pixels are disposed between the first transmission region and the second transmission region.

15 . The display device of claim 11 , wherein the dummy pixels surround the first transmission region and the second transmission region.

16 . The display device of claim 11 , wherein a width of the second transmission region is different from a width of the first transmission region.

17 . The display device of claim 16 ,
wherein the width of the non-display area in a second direction across the first direction, between the first transmission region and the second transmission region, is smaller than a width of the second transmission region in the second direction.

18 . The display device of claim 11 , wherein each of emitting pixels comprises a pixel circuit and a display element, the pixel circuit comprising at least one transistor, the display element being electrically connected to the pixel circuit,
wherein each of dummy pixels comprises a dummy pixel circuit comprising at least one dummy transistor, and wherein a structure of the pixel circuit is same as a structure of the dummy pixel circuit.

19 . The display device of claim 17 , further comprising a pixel defining layer arranged on the pixel circuit and the dummy pixel circuit,
wherein the pixel defining layer comprises an opening corresponding to each of emitting pixels, and wherein the pixel defining layer has a flat surface overlapping the dummy pixels.

20 . The display device of claim 11 , further comprising electrode voltage lines intersecting the driving voltage lines and electrically connected to the driving voltage lines via contact holes to form a conductive mesh structure.

Assignees

• Samsung Display Co Ltd

Inventors

• Yoon Youngsoo
• Kim Jaewon
• Park Hyunae
• Park Hyungjun
• Sung Seungwoo
• Um Nuree
• Youn Ilgoo
• Lee Jieun
• Jang Donghyeon
• Jo Seunghan

Classifications

• H10K59/1216

  the pixel elements being capacitors · CPC title

• H10K59/1213

  the pixel elements being TFTs · CPC title

• H10K59/131 Primary

  Interconnections, e.g. wiring lines or terminals · CPC title

• H10K59/122

  Pixel-defining structures or layers, e.g. banks · CPC title

• G09G3/3233

  with pixel circuitry controlling the current through the light-emitting element · CPC title