Display substrate, manufacturing method therefor, and display apparatus

Patent metadata

Field	Value
Publication number	US-2026013346-A1
Application number	US-202418881746-A
Country	US
Kind code	A1
Filing date	Apr 18, 2024
Priority date	May 11, 2023
Publication date	Jan 8, 2026
Grant date	—

Abstract

A display substrate, a manufacturing method therefor, and a display apparatus. The display substrate comprises a plurality of sub-pixels; each sub-pixel comprises a pixel drive circuit; each pixel drive circuit at least comprises a first transistor, a second transistor, a third transistor and a fourth transistor; a first electrode of the first transistor is connected to a data signal line, and a second electrode of the first transistor is connected to a gate of a fourth transistor; a first electrode of the second transistor is connected to a first power line, and a second electrode of the second transistor is connected to a first electrode of the fourth transistor; a first electrode of each third transistor is connected to a second power line, and a second electrode of the third transistor is connected to a second electrode of the fourth transistor.

First claim

1 . A display substrate comprising a plurality of sub-pixels forming a plurality of pixel rows and a plurality of pixel columns, wherein:
at least one sub-pixel comprises a pixel drive circuit at least comprising a first transistor, a second transistor, a third transistor, and a fourth transistor, a first electrode of the first transistor is connected to a data signal line, a second electrode of the first transistor is connected to a gate electrode of the fourth transistor, a first electrode of the second transistor is connected to a first power supply line, a second electrode of the second transistor is connected to a first electrode of the fourth transistor, a first electrode of the third transistor is connected to a second power supply line, a second electrode of the third transistor is connected to a second electrode of the fourth transistor; and in the at least one sub-pixel, along a direction of a pixel row, the sub-pixel has a pixel width, and there is an inter-electrode distance between the first electrode of the first transistor and the second electrode of the first transistor, and the inter-electrode distance is greater than or equal to 0.5*the pixel width.

2 . The display substrate according to claim 1 , wherein the inter-electrode distance is greater than or equal to 0.85 μm.

3 . The display substrate according to claim 1 , wherein along the direction of the pixel row, there is a first distance between the first electrode of the first transistor and the data signal line, there is a second distance between the second electrode of the first transistor and the data signal line, and the second distance is greater than the first distance.

4 . The display substrate according to claim 3 , wherein the second distance is greater than or equal to 5*the first distance.

5 . The display substrate according to claim 1 , wherein in the at least one sub-pixel, the first transistor at least comprises a first active layer, the first active layer is in a shape of a strip extending along the direction of the pixel row, the first active layer at least comprises a first region and a second region, and the first region of the first active layer and the second region of the first active layer are arranged in sequence along the direction of the pixel row.

6 . The display substrate according to claim 5 , wherein the at least one sub-pixel further comprises a data connection electrode and an inter-electrode connection electrode;
a first end of the data connection electrode is connected to the first region of the first active layer through a first via; a second end of the data connection electrode is connected to the data signal line; a first end of the inter-electrode connection electrode is connected to the second region of the first active layer through a second via, and a second end of the inter-electrode connection electrode is connected to the gate electrode of the fourth transistor; and the inter-electrode distance between the first electrode of the first transistor and the second electrode of the first transistor is a distance between a geometric center of the first via and a geometric center of the second via, a first distance between the first electrode of the first transistor and the data signal line is a distance between the geometric center of the first via and an edge of the data signal line on a side close to the first transistor, and a second distance between the second electrode of the first transistor and the data signal line is a distance between the geometric center of the second via and the edge of the data signal line on the side close to the first transistor.

7 . The display substrate according to claim 5 , wherein in the at least one sub-pixel, the second transistor at least comprises a second active layer, the third transistor at least comprises a third active layer, and the fourth transistor at least comprises a fourth active layer; and the second active layer, the third active layer, and the fourth active layer are connected to each other to form an integral structure.

8 . The display substrate according to claim 7 , wherein in at least one pixel column, second active layers of two adjacent sub-pixels are connected to each other to form an integral structure.

9 . The display substrate according to claim 1 , wherein in at least one pixel column, pixel drive circuits of two adjacent sub-pixels are mirror-symmetrical with respect to a pixel centerline, and the pixel centerline is a straight line between two adjacent pixel rows and extending along the direction of the pixel row.

10 . The display substrate according to claim 1 , wherein, in the at least one sub-pixel, the pixel drive circuit further comprises a first storage capacitor and a second storage capacitor;
the first storage capacitor comprises a first electrode plate and a second electrode plate, an orthographic projection of the first electrode plate on a plane of the display substrate at least partially overlaps with an orthographic projection of the second electrode plate on the plane of the display substrate, the first electrode plate is connected to the gate electrode of the fourth transistor, and the second electrode plate is connected to the first electrode of the fourth transistor; and the second storage capacitor comprises a third electrode plate and a fourth electrode plate, an orthographic projection of the third electrode plate on the plane of the display substrate at least partially overlaps with an orthographic projection of the fourth electrode plate on the plane of the display substrate, the third electrode plate is connected to the first electrode of the fourth transistor, and the fourth electrode plate is connected to the first power supply line.

11 . The display substrate according to claim 10 , wherein in the at least one sub-pixel, an orthographic projection of at least one of the first electrode plate, the second electrode plate, the third electrode plate, and the fourth electrode plate on the plane of the display substrate does not overlap with an orthographic projection of the data signal line on the plane of the display substrate.

12 . The display substrate according to claim 1 , wherein in the at least one sub-pixel, an orthographic projection of the first power supply line on a plane of the display substrate does not overlap with an orthographic projection of the data signal line on the plane of the display substrate.

13 . The display substrate according to claim 1 , wherein the at least one sub-pixel further comprises at least one power supply connection line, the power supply connection line is in a shape of a line extending along the direction of the pixel row, the first power supply line is in a shape of a line extending along a direction of a pixel column, and the first power supply line and the power supply connection line are connected to form a mesh structure for transmitting a first power supply signal.

14 . The display substrate according to claim 1 , wherein in a direction perpendicular to the display apparatus, the display substrate at least comprises a first conductive layer, a second conductive layer, and a third conductive layer that are disposed in sequence on a silicon base substrate, the silicon base substrate at least comprises active layers of the first transistor to the fourth transistor, the first conductive layer at least comprises gate electrodes of the first transistor to the fourth transistor, the second conductive layer at least comprises the first electrode and the second electrode of the first transistor, and the third conductive layer at least comprises the data signal line.

15 . The display sub

Assignees

• Yunnan Invensight Optoelectronics Technology Co Ltd
• Boe Technology Group Co Ltd
• Beijing Boe Technology Dev Co Ltd

Inventors

• Jiang Shanghong
• Shan Qingshan
• Yang Shengji
• Lu Pengcheng
• Bai Xiao
• Fan Longfei
• Zhang Dacheng

Classifications

• H10K59/1201

  Manufacture or treatment · CPC title

• H10K59/1216

  the pixel elements being capacitors · CPC title

• H10K59/1213 Primary

  the pixel elements being TFTs · CPC title

• H10K59/131 Primary

  Interconnections, e.g. wiring lines or terminals · CPC title

• H10K71/00

  Manufacture or treatment specially adapted for the organic devices covered by this subclass · CPC title