Pixel circuit and display panel
US-2024428730-A1 · Dec 26, 2024 · US
US2026013328A1 · US · A1
| Field | Value |
|---|---|
| Publication number | US-2026013328-A1 |
| Application number | US-202519061101-A |
| Country | US |
| Kind code | A1 |
| Filing date | Feb 24, 2025 |
| Priority date | Jul 3, 2024 |
| Publication date | Jan 8, 2026 |
| Grant date | — |
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A display device includes a circuit layer including light-emitting pixel drivers; a first sharing line next to a first boundary between a first light-emitting pixel driver and a second light-emitting pixel driver next to each other, and electrically connected to the first light-emitting pixel driver and the second light-emitting pixel driver; a first semiconductor layer on a substrate; and a second semiconductor layer on a first inter-insulating layer. Each of the light-emitting pixel drivers includes a first transistor of which a channel portion, a first electrode, and a second electrode are disposed in the second semiconductor layer. A first semiconductor layer and a second semiconductor layer of the first light-emitting pixel driver are symmetrical with a first semiconductor layer and a second semiconductor layer of the second light-emitting pixel driver with respect to the first boundary.
Opening claim text (preview).
What is claimed is: 1 . A display device comprising: a substrate including a display area in which light-emitting areas are arranged, and a non-display area disposed around the display area; a circuit layer disposed on the substrate, the circuit layer including: light-emitting pixel drivers arranged in a first direction and a second direction; a first sharing line extending in the second direction, next to a first boundary between a first light-emitting pixel driver and a second light-emitting pixel driver next to each other in the first direction among the light-emitting pixel drivers, and electrically connected to the first light-emitting pixel driver and the second light-emitting pixel driver; a first semiconductor layer disposed on the substrate; a first gate insulating layer covering the first semiconductor layer; a first gate conductive layer disposed on the first gate insulating layer; a second gate insulating layer covering the first gate conductive layer; a second gate conductive layer disposed on the second gate insulating layer; a first inter-insulating layer covering the second gate conductive layer; and a second semiconductor layer disposed on the first inter-insulating layer; and an element layer disposed on the circuit layer and including light-emitting elements each disposed in the light-emitting areas and electrically connected to the light-emitting pixel drivers, wherein one of the light-emitting pixel drivers includes a first transistor which generates a driving current for one of the light-emitting elements, a channel portion, a first electrode, and a second electrode of the first transistor are disposed in the second semiconductor layer, and a first semiconductor layer and a second semiconductor layer of the first light-emitting pixel driver are symmetrical with a first semiconductor layer and a second semiconductor layer of the second light-emitting pixel driver with respect to the first boundary. 2 . The display device of claim 1 , wherein the light-emitting pixel drivers further include: a third light-emitting pixel driver next to the second light-emitting pixel driver in the first direction; a fourth light-emitting pixel driver next to the first light-emitting pixel driver in the second direction; a fifth light-emitting pixel driver next to the second light-emitting pixel driver in the second direction; and a sixth light-emitting pixel driver next to the third light-emitting pixel driver in the second direction, the first semiconductor layer and the second semiconductor layer of the second light-emitting pixel driver are symmetrical with a first semiconductor layer and a second semiconductor layer of the third light-emitting pixel driver with respect to a second boundary between the second light-emitting pixel driver and the third light-emitting pixel driver, the first semiconductor layer and the second semiconductor layer of the first light-emitting pixel driver are symmetrical with a first semiconductor layer and a second semiconductor layer of the fourth light-emitting pixel driver with respect to a third boundary between the first light-emitting pixel driver and the fourth light-emitting pixel driver, the first semiconductor layer and the second semiconductor layer of the second light-emitting pixel driver are symmetrical with a first semiconductor layer and a second semiconductor layer of the fifth light-emitting pixel driver with respect to an extension line of the third boundary, and the first sharing line is further electrically connected to the fourth light-emitting pixel driver and the fifth light-emitting pixel driver. 3 . The display device of claim 2 , wherein the circuit layer further includes: a data line transmitting a data signal to the light-emitting pixel drivers; a reference voltage line transmitting a reference voltage to the light-emitting pixel drivers; an initialization voltage line transmitting an initialization voltage to the light-emitting pixel drivers; a first power line transmitting a first power to the light-emitting pixel drivers; a scan write line transmitting a scan write signal to the light-emitting pixel drivers; a reset control line transmitting a reset control signal to the light-emitting pixel drivers; a bias control line transmitting a bias control signal to the light-emitting pixel drivers; a first emission control line transmitting a first emission control signal to the light-emitting pixel drivers; and a second emission control line transmitting a second emission control signal to the light-emitting pixel drivers. 4 . The display device of claim 3 , wherein the circuit layer further includes: a third gate insulating layer covering the second semiconductor layer; a third gate conductive layer disposed on the third gate insulating layer; a second inter-insulating layer covering the third gate conductive layer; a first source drain conductive layer disposed on the second inter-insulating layer; a first planarization layer covering the first source drain conductive layer; a second source drain conductive layer disposed on the first planarization layer; and a second planarization layer covering the second source drain conductive layer, and the one of the light-emitting pixel drivers includes: a second transistor electrically connected between a gate electrode of the first transistor and the data line; a third transistor electrically connected between the gate electrode of the first transistor and the reference voltage line; a fourth transistor electrically connected between one of the light-emitting elements and the initialization voltage line; a fifth transistor electrically connected between the first electrode of the first transistor and the first power line; a sixth transistor electrically connected between the second electrode of the first transistor and the one of the light-emitting elements; a first capacitor electrically connected between the gate electrode of the first transistor and the second electrode of the first transistor; and a second capacitor electrically connected between the first power line and the second electrode of the first transistor. 5 . The display device of claim 4 , wherein the first power line includes: a first power main line disposed on the third gate conductive layer and extending in the first direction; and a first power sub-line disposed on the second source drain conductive layer and extending in the second direction, and the first sharing line includes the first power sub-line. 6 . The display device of claim 5 , wherein the circuit layer further includes: an electrode extending portion extending from a first electrode of the sixth transistor; a first capacitor electrode disposed on the first gate conductive layer, overlapping a portion of the electrode extending portion, and electrically connected to the gate electrode of the first transistor; a second capacitor electrode disposed on the second gate conductive layer, overlapping the first capacitor electrode, and electrically connected to the second electrode of the first transistor; a third capacitor electrode disposed on the first gate conductive layer, spaced apart from the first capacitor electrode, overlapping another portion of the electrode extending portion and the second capacitor electrode, and electrically connected to the first power line; a first power connection auxiliary electrode disposed on the first source drain conductive layer and electrically connected to the third capacitor electrode and the first power main line; and a second power connection auxiliary electrode disposed on the first source drain conductive layer and electrically connected to a first electrode of the fifth transistor and the first power main line, a third capacit
the pixel elements being capacitors · CPC title
comprising structures specially adapted for lowering the resistance · CPC title
with pixel circuitry controlling the current through the light-emitting element · CPC title
Interconnections, e.g. wiring lines or terminals · CPC title
the pixel elements being TFTs · CPC title
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