Memory device and method of performing a program operation

Patent metadata

Field	Value
Publication number	US-2026011371-A1
Application number	US-202519256682-A
Country	US
Kind code	A1
Filing date	Jul 1, 2025
Priority date	Jul 3, 2024
Publication date	Jan 8, 2026
Grant date	—

Abstract

A memory device includes a memory cell array including a plurality of memory cells coupled to a word line. The memory device also includes a peripheral circuit configured to perform a program operation including a plurality of program loops including a program pulse apply operation and a verify operation. The memory device further includes control logic configured to control the peripheral circuit to determine a voltage level of fixed program pulses applied to memory cells having a same target threshold voltage based on the target threshold voltage and a number of program loops performed among the plurality of program loops, and to perform a verify operation on memory cells passing verification in a previous program loop performed prior to a current program loop being performed among the plurality of memory cells in the current program loop.

First claim

What is claimed is:

1 . A memory device, comprising:
a memory cell array including a plurality of memory cells coupled to a word line; a peripheral circuit configured to perform a program operation including a plurality of program loops including a program pulse apply operation of applying program pulses to the plurality of memory cells to increase threshold voltages of the plurality of memory cells, and a verify operation of detecting whether the threshold voltages of the plurality of memory cells reach a target level prior to performing the program pulse apply operation; and control logic configured to control the peripheral circuit to determine a voltage level of fixed program pulses applied to memory cells having a same target threshold voltage based on the target threshold voltage and a number of program loops performed among the plurality of program loops, and to perform a verify operation on memory cells passing verification in a previous program loop performed prior to a current program loop being performed among the plurality of memory cells in the current program loop.

2 . The memory device of claim 1 , wherein the voltage level of the fixed program pulses is determined as a sum of a base program level and an offset program level, and
wherein the control logic is configured to determine the base program level based on the target threshold voltage and determine the offset program level based on the number of program loops performed.

3 . The memory device of claim 2 , wherein the control logic is configured to decrease the offset program level in response to an increase in the number of program loops performed.

4 . The memory device of claim 2 , wherein the control logic is configured to determine the offset program level based on a width of a threshold voltage distribution corresponding to the target threshold voltage.

5 . The memory device of claim 4 , wherein the control logic is configured to decrease the offset program level as the width of the threshold voltage distribution decreases.

6 . The memory device of claim 2 , wherein the control logic is configured to increase both the base program level and the offset program level in response to an increase in the target threshold voltage.

7 . The memory device of claim 1 , wherein a level of a verify voltage corresponding to the target threshold voltage is determined as a difference between a base verify level and an offset verify level, and
wherein the control logic is configured to determine the base verify level based on the target threshold voltage and determine the offset verify level based on the number of program loops performed.

8 . The memory device of claim 7 , wherein the control logic is configured to decrease the offset verify level in response to an increase in the number of program loops performed.

9 . The memory device of claim 7 , wherein the control logic is configured to determine the offset verify level based on a width of a threshold voltage distribution corresponding to the target threshold voltage.

10 . The memory device of claim 9 , wherein the control logic is configured to decrease the offset verify level as the width of the threshold voltage distribution decreases.

11 . The memory device of claim 7 , wherein the control logic is configured to increase both the base verify level and the offset verify level in response to an increase in the target threshold voltage.

12 . A method of operating a memory device, the method comprising:
performing a verify operation to detect whether threshold voltages of a plurality of memory cells coupled to a selected word line reach a target level by applying verify voltages to the plurality of memory cells; determining a voltage level of fixed program pulses to be applied to memory cells having a same target threshold voltage based on the threshold voltages and a number of program loops performed; and performing a program pulse apply operation to increase the threshold voltages of the plurality of memory cells by applying the fixed program pulses to the plurality of memory cells, wherein the verify operation is performed on memory cells passing verification and memory cells failing the verification in a previous program loop performed prior to a current program loop being performed.

13 . The method of claim 12 , wherein levels of the verify voltages comprises a base verify level and an offset verify level, and
wherein performing the verify operation comprises: determining the base verify level based on the target threshold voltage; determining the offset verify level based on the number of program loops performed or a width of a threshold voltage distribution corresponding to the target threshold voltage; and determining a difference between the base verify level and the offset verify level as the level of the verify voltages corresponding to the target threshold voltage.

14 . The method of claim 13 , wherein determining the offset verify level comprises decreasing the offset verify level as the number of program loops performed increases or the width of the threshold voltage distribution decreases.

15 . The method of claim 13 , wherein the base verify level and the offset verify level increase as the target threshold voltage increases.

16 . The method of claim 12 , wherein the voltage level of the fixed program pulses includes a base program level and an offset program level, and
wherein determining the voltage level of the fixed program pulses comprises: determining the base program level based on the target threshold voltage; determining the offset program level based on the number of program loops performed or a width of a threshold voltage distribution corresponding to the target threshold voltage; and determining a sum of the base program level and the offset program level as the voltage level of the fixed program pulses corresponding to the target threshold voltage.

17 . The method of claim 16 , wherein determining the offset program level comprises decreasing the offset program level as the number of program loops performed increases or the width of the threshold voltage distribution decreases.

18 . The method of claim 16 , wherein the base program level and the offset program level increase as the target threshold voltage increases.

19 . The method of claim 12 , wherein performing the program pulse apply operation comprises applying a program inhibit voltage to memory cells determined based on a result of the verify operation when the fixed program pulses are applied.

Assignees

• Sk Hynix Inc

Inventors

• Kim Jae Woong
• Park In Su
• Jang Jung Shik
• Jung Dong Jae
• Jo Young Hwa
• Choi Jung Dal

Classifications

• G11C16/3459

  Circuits or methods to verify correct programming of nonvolatile memory cells · CPC title

• G11C16/10 Primary

  Programming or data input circuits · CPC title

• G11C16/0483

  comprising cells having several storage transistors connected in series · CPC title

• G11C11/5628

  Programming or writing circuits; Data input circuits · CPC title