Display device

Patent metadata

Field	Value
Publication number	US-2026006920-A1
Application number	US-202519322140-A
Country	US
Kind code	A1
Filing date	Sep 8, 2025
Priority date	Feb 27, 2020
Publication date	Jan 1, 2026
Grant date	—

Abstract

A display device includes a first region and a second region each including a plurality of pixels, and a plurality of wires connected to the plurality of pixels, respectively, to transmit a signal, where the number of pixels per unit area in the second region is less than the number of pixels per unit area in the first region, and the number of wires per unit area in the second region is less than the number of wires per unit area in the first region.

First claim

What is claimed is:

1 . A display device, comprising:
a substrate; a polycrystalline semiconductor layer on the substrate, the polycrystalline semiconductor layer including a channel, a first electrode, and a second electrode of a first transistor(T 1 ); a first gate conductor layer including a gate electrode of the first transistor overlapping the channel of the first transistor, and a first electrode of a boost capacitor; an oxide semiconductor layer on the substrate, the oxide semiconductor layer including a channel, a first electrode, a second electrode of a second transistor(T 3 ), and a second electrode of a boost capacitor; a second gate conductor layer including a lower gate electrode of the second transistor overlapping the channel of the second transistor; a third gate conductor layer including an upper gate electrode of the second transistor overlapping the channel of the second transistor; and a first data conductor layer including a first connection electrode electrically connected to the second electrode of the second transistor and the gate electrode of the first transistor, wherein the first connection electrode overlaps the boost capacitor.

2 . The display device of claim 1 , wherein
the first gate conductor layer further comprises a first scan line extended to the first electrode of the boost capacitor.

3 . The display device of claim 2 , wherein
the first connection electrode is connected to the second electrode of the boost capacitor through an opening, and the opening overlaps the first scan line.

4 . The display device of claim 2 , wherein
the first connection electrode is connected to the second electrode of the boost capacitor through an opening, and the opening does not overlap the first scan line.

5 . The display device of claim 1 , wherein
the oxide semiconductor layer further includes a channel, a first electrode, and a second electrode of a third transistor(T 4 ), a second gate conductor layer further includes a lower gate electrode of the third transistor overlapping the channel of the third transistor(T 4 ), a third gate conductor layer further includes an upper gate electrode of the third transistor overlapping the channel of the third transistor(T 4 ), and the second electrode of the boost capacitor is disposed between the second transistor and the third transistor.

6 . The display device of claim 1 , wherein
the polycrystalline semiconductor layer further comprises a channel, a first electrode, and a second electrode of a fourth transistor, the first gate conductor layer further comprises a gate electrode of the fourth transistor overlapping the channel of the fourth transistor, the third gate conductor layer further comprises an initialization voltage line electrically connected to the fourth transistor, and the first data conductor layer further comprises an initialization voltage supply line electrically connected to the initialization voltage line.

7 . The display device of claim 6 , wherein
the initialization voltage supply line is branched left and right at the crossing part with the initialization voltage line in a plan view.

8 . The display device of claim 1 , further comprising:
a light blocking member disposed on the substrate, wherein the light blocking member is disposed between the substrate and the gate electrode of the first transistor.

9 . A display device, comprising:
a substrate; a polycrystalline semiconductor layer on the substrate, the polycrystalline semiconductor layer including a channel, a first electrode, and a second electrode of a first transistor(T 1 ); a first gate conductor layer including a gate electrode of the first transistor overlapping the channel of the first transistor, and a first electrode of a boost capacitor; an oxide semiconductor layer on the substrate, the oxide semiconductor layer including a channel, a first electrode, and a second electrode of a second transistor(T 3 ), and a second electrode of a boost capacitor; a second gate conductor layer including a lower gate electrode of the second transistor overlapping the channel of the second transistor; a third gate conductor layer including an upper gate electrode of the second transistor overlapping the channel of the second transistor; and a first data conductor layer including a first connection electrode electrically connected to the second electrode of the second transistor and the gate electrode of the first transistor, wherein the first connection electrode is connected to the second electrode of the boost capacitor through an opening.

10 . The display device of claim 9 , wherein
the first gate conductor layer further comprises a first scan line connected to the first electrode of the boost capacitor.

11 . The display device of claim 10 , wherein
the opening overlaps the first scan line.

12 . The display device of claim 10 , wherein
the opening does not overlap the first scan line.

13 . The display device of claim 9 , wherein
the oxide semiconductor layer further includes a channel, a first electrode, and a second electrode of a third transistor(T 4 ), the second gate conductor layer further includes a lower gate electrode of the third transistor(T 4 ) overlapping the channel of the third transistor(T 4 ), the third gate conductor layer further includes an upper gate electrode of the third transistor(T 4 ) overlapping the channel of the third transistor(T 4 ), and the second electrode of the boost capacitor is disposed between the second transistor and the third transistor.

14 . The display device of claim 9 , wherein
the polycrystalline semiconductor layer further comprises a channel, a first electrode, and a second electrode of a fourth transistor, the first gate conductor layer further comprises a gate electrode of the fourth transistor overlapping the channel of the fourth transistor, the third gate conductor layer further comprises an initialization voltage line electrically connected to the fourth transistor, and the first data conductor layer further comprises an initialization voltage supply line electrically connected to the initialization voltage line.

15 . The display device of claim 14 , wherein
the initialization voltage supply line is branched left and right at the crossing part with the initialization voltage line in a plan view.

16 . The display device of claim 15 , further comprising:
a light emitting diode connected between a driving voltage line and a common voltage line; a fifth transistor connected between the first electrode of the first transistor and a data line, the first electrode of the first transistor being connected to the driving voltage line; and a storage capacitor connected between the driving voltage line and the gate electrode of the first transistor.

17 . The display device of claim 9 , further comprising:
a light blocking member disposed on the substrate, wherein the light blocking member is disposed between the substrate and the gate electrode of the first transistor.

Assignees

• Samsung Display Co Ltd

Inventors

• Kim Dong-Hwi
• Jeon Jin

Classifications

• H10D86/441

  Interconnections, e.g. scanning lines · CPC title

• H10H29/142

  Two-dimensional arrangements, e.g. asymmetric LED layout · CPC title

• H10K59/1216

  the pixel elements being capacitors · CPC title

• H10K59/1213

  the pixel elements being TFTs · CPC title

• H10K59/131

  Interconnections, e.g. wiring lines or terminals · CPC title