Semiconductor devices having highly integrated capacitors therein

Patent metadata

Field	Value
Publication number	US-2025393194-A1
Application number	US-202519316961-A
Country	US
Kind code	A1
Filing date	Sep 2, 2025
Priority date	Jan 6, 2022
Publication date	Dec 25, 2025
Grant date	—

Abstract

A semiconductor device includes a vertical stack of ring-shaped electrodes that are electrically connected together into a top electrode of a capacitor, on a semiconductor substrate. A bottom electrode of the capacitor is also provided, which extends vertically in a direction orthogonal to a surface of the substrate and through centers of the vertical stack of ring-shaped electrodes. An electrically insulating bottom supporting pattern is provided, which extends between a lowermost one of the ring-shaped electrodes and an intermediate one of the ring-shaped electrodes.

First claim

1 .- 31 . (canceled)

32 . A method of fabricating a semiconductor device, comprising:
forming a mold layer; forming a preliminary top supporting layer on the mold layer; etching the mold layer and the preliminary top supporting layer to form a conductive contact hole; forming a bottom electrode layer filling at least a portion of the conductive contact hole; removing a portion of the bottom electrode layer to form a bottom electrode; removing the mold layer; forming a dielectric layer on the bottom electrode; and forming a top electrode on the dielectric layer, wherein a level of a bottom surface of the preliminary top supporting layer is higher than a level of a top surface of the bottom electrode.

33 . The method of claim 32 , wherein forming the bottom electrode layer comprises forming a seam in the bottom electrode layer, and
wherein removing the portion of the bottom electrode layer comprises exposing the seam.

34 . The method of claim 33 , wherein removing the portion of the bottom electrode layer further comprises forming a recess defined by the top surface of the bottom electrode, and
wherein the recess is connected to the seam.

35 . The method of claim 33 , further comprising forming a top supporting layer filling the seam.

36 . The method of claim 35 , further comprising etching the top supporting layer to form a penetration hole,
wherein the mold layer is removed through the penetration hole.

37 . The method of claim 32 , wherein removing the portion of the bottom electrode layer comprises exposing a portion of a sidewall of the mold layer.

38 . The method of claim 37 , further comprising forming a top supporting layer covering the portion of the sidewall of the mold layer and the top surface of the bottom electrode.

39 . The method of claim 32 , wherein a level of a top surface of the mold layer is higher than the level of the top surface of the bottom electrode.

40 . The method of claim 32 , wherein the top surface of the bottom electrode is an uppermost portion of the bottom electrode.

41 . The method of claim 32 , further comprising forming a top supporting pattern comprising a first portion on the top surface of the bottom electrode, and a second portion filling an internal space of the bottom electrode.

42 . A method of fabricating a semiconductor device, comprising:
forming a mold layer; forming a preliminary top supporting layer on the mold layer; etching the mold layer and the preliminary top supporting layer to form a conductive contact hole; forming a bottom electrode layer filling at least a portion of the conductive contact hole; removing a portion of the bottom electrode layer to form a bottom electrode; removing the mold layer; forming a dielectric layer on the bottom electrode; and forming a top electrode on the dielectric layer, wherein forming the bottom electrode layer comprises forming a seam in the bottom electrode layer, and wherein removing the portion of the bottom electrode layer comprises exposing the seam.

43 . The method of claim 42 , further comprising forming a top supporting layer filling the seam,
wherein the top supporting layer covers a top surface of the bottom electrode.

44 . The method of claim 43 , further comprising forming a penetration hole penetrating the top supporting layer,
wherein the penetration hole exposes the top surface of the bottom electrode.

45 . The method of claim 44 , wherein the mold layer is removed through the penetration hole.

46 . The method of claim 42 , wherein the bottom electrode layer covers a sidewall of the preliminary top supporting layer and a sidewall of the mold layer, and
wherein removing the portion of the bottom electrode layer comprises exposing the sidewall of the preliminary top supporting layer and a portion of the sidewall of the mold layer.

47 . The method of claim 42 , wherein the bottom electrode layer surrounds the seam.

48 . A method of fabricating a semiconductor device, comprising:
forming a mold layer; forming a preliminary top supporting layer on the mold layer; etching the mold layer and the preliminary top supporting layer to form a conductive contact hole; forming a bottom electrode layer filling at least a portion of the conductive contact hole; removing a portion of the bottom electrode layer to form a bottom electrode; removing the mold layer; forming a dielectric layer on the bottom electrode; and forming a top electrode on the dielectric layer, wherein the bottom electrode layer covers a sidewall of the mold layer, and wherein removing the portion of the bottom electrode layer comprises exposing a portion of the sidewall of the mold layer.

49 . The method of claim 48 , wherein a level of a top surface of the bottom electrode is lower than a level of a top surface of the mold layer.

50 . The method of claim 48 , further comprising forming a top supporting layer covering a top surface of the bottom electrode and the portion of the sidewall of the mold layer.

51 . The method of claim 50 , wherein the top supporting layer comprises a portion extending into an internal space of the bottom electrode.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Lim Jung-Bum
• Kim Seungjin
• Yang Sangchul
• Lee Jeon Il
• Lee Hoin

Classifications

• H10W20/435 Primary

  Cross-sectional shapes or dispositions of interconnections · CPC title

• H10D1/696

  comprising multiple layers, e.g. comprising a barrier layer and a metal layer (barrier layers to prevent diffusion of hydrogen or oxygen in perovskite based capacitors H10D1/688) · CPC title

• H10D1/716 Primary

  having vertical extensions · CPC title

• H10D1/043

  using patterning processes to form electrode extensions, e.g. etching · CPC title

• H10D1/042

  using deposition processes to form electrode extensions · CPC title