Integrated Circuits for Driving Transducers

Patent metadata

Field	Value
Publication number	US-2025392868-A1
Application number	US-202519306813-A
Country	US
Kind code	A1
Filing date	Aug 21, 2025
Priority date	Mar 25, 2022
Publication date	Dec 25, 2025
Grant date	—

Abstract

An integrated circuit (IC), comprising: a first transducer driver for driving a first transducer; a second transducer driver for driving a second transducer; and boost circuitry comprising first and second boost nodes, the boost converter configurable to boost a supply voltage received at one or more input pins of the IC to provide first and second boosted voltages to respective first and second transducer drivers via respective first and second boost nodes.

First claim

1 .- 22 . (canceled)

23 . An integrated circuit (IC), comprising:
a first transducer driver for driving a first transducer; a second transducer driver for driving a second transducer; and boost circuitry comprising first and second boost nodes, the boost converter configurable to boost a supply voltage received at one or more input pins of the IC to provide first and second boosted voltages to respective first and second transducer drivers via respective first and second boost nodes, control circuitry configured to switch the boost circuitry between a first topology and a second topology in dependence on one or more of the following: a) a signal to be output to the first transducer; b) a signal to be output to the second transducer; c) one or more operational limits of the IC; d) a power level available to the IC e) one or more external components connected to the IC for use with the boost circuitry.

24 . The IC of claim 23 , wherein, in one of the first and second topologies, power is supplied to each of the first and second transducer drivers via both of the first and second boost nodes.

25 . The IC of claim 23 , wherein, in one of the first and second topologies, power is supplied to the first transducer driver via the first boost node and to the second transducer driver via the second boost node.

26 . The IC of claim 23 , wherein the control circuitry is configured to switch the boost circuitry between the first topology and the second topology in dependence on a load or thermal condition exceeding a predetermined threshold.

27 . The IC of claim 23 , wherein the control circuitry is configured to switch the boost circuitry between the first and second topologies on determining that an efficiency of the boost circuitry is below a predetermined efficiency threshold.

28 . The IC of claim 23 , wherein the switching comprises enabling one or more components of the boost circuitry to improve efficiency of the boost circuitry.

29 . The IC of claim 23 , wherein the boost circuitry comprises:
a first boost stage configured to boost the supply voltage to the first boosted voltage at the first boost node; and a second boost stage configured to boost the supply voltage to the second boosted voltage on the second boost node.

30 . The IC of claim 29 , wherein, in response to detection of the load or thermal condition exceeding the predetermined threshold, the control circuitry is configured to disable one of the first and second boost stages when switching between the first and second topologies.

31 . The IC of claim 29 , wherein the first and second boosted voltages are equal, and wherein the first and second boost nodes are coupled to a common output node.

32 . The IC of claim 29 , wherein the first and second boosted voltages are different, and the first and second boost nodes are isolated from one another.

33 . The IC of claim 29 , wherein in the first topology the first boost stage is configured to be coupled to a first inductor external to the IC via a first one of the input pins of the IC and wherein the second boost stage is configured to be coupled to a second inductor external to the IC via a second one of the input pins of the IC.

34 . The IC of claim 29 , wherein in the second topology, the first and second boost stage are configured to be coupled to a first inductor external to the IC via a first one of the input pins of the IC.

35 . The IC of claim 29 , wherein the control circuitry is configured to control the first boost stage in antiphase to the second boost stage.

36 . The IC of claim 29 , wherein the control circuitry is configured to control the first and second boost stages using a common control loop.

37 . The IC of claim 29 , wherein in the first topology, the first boost stage is configured to provide the first boosted voltage to the first transducer driver and the second boost stage is configured to provide the second boosted voltage to the second transducer stage, and in the second topology, the first boost stage is configured to provide the first boosted voltage to the first transducer driver and the second transducer driver.

38 . The IC of claim 37 , wherein the control circuitry is configured to hold the second boost stage in a low-power mode when the boost circuitry is switch to the second topology.

39 . The IC of claim 29 , wherein in a first topology, the first and second boosted voltages are equal, and wherein the first and second boost nodes are coupled to a common output node, and in the second topology, the first and second boosted voltages are different, and the first and second boost nodes are isolated from one another.

40 . The IC of claim 23 , wherein the control circuitry is configured to dynamically adjust one or more current limits for each of the first and second transducer drivers in dependence on a total current limit for the IC.

41 . The IC of claim 23 , comprising a signal processor configure to:
receive an input signal; generate first and second channel signals based on the received input signal; and provide the first and second channel signals to respective first and second transducer drivers, wherein the boost circuitry is controlled in dependence on the first and second channel signals.

42 . The IC of claim 41 , wherein the first boosted voltage is controlled to track a parameter of the first channel signal, and wherein the second boosted voltage is controlled to track a parameter of the second channel signal.

43 . The IC of claim 23 , wherein the boost circuitry comprises:
a first switching device coupled between a first inductor node and the first boost node; a second switching device coupled between the first inductor node and a ground reference voltage; a third switching device coupled between a second inductor node and the second boost node; and a fourth switching device coupled between the second inductor node and the ground reference voltage.

44 . The IC of claim 29 , wherein the first boosted voltage and/or the second boosted voltage is controlled in dependence on an output of the first transducer driver and/or the second transducer driver.

45 . The IC of claim 23 , wherein the boost circuitry comprises inductive boost circuitry and/or capacitive boost circuitry.

46 . The IC of claim 23 , wherein the first and second transducer drivers are configured to drive a transducer as a bridge-tied load.

47 . The IC of claim 23 , wherein the IC is an audio IC and the first and second transducers are audio transducers.

48 . The IC of claim 23 , wherein the IC is a haptic IC and the first and second transducers are haptic transducers.

49 . A system comprising:
the IC of claim 23 ; and the first and second transducers.

50 . The system of claim 49 , further comprising:
one or more inductors coupled to the boost circuitry, each inductor coupled to the boost circuitry via a respective inductor pin of the IC; and/or one or more capacitors coupled to the boost circuitry, each capacitor coupled to the boost circuitry via a respective capacitor pin of the IC.

51 . An electronic device comprising the IC of claim 23 , wherein the device comprises one of a wearable device, a vehicle, a mobile computing device, a laptop computer, a tablet computer, a games console, a remote-control device, a home automation controller or

Assignees

• Cirrus Logic Int Semiconductor Ltd

Inventors

• Morgan Ross C
• Robinson Michael
• Tyagi Itisha

Classifications

• H04R5/02

  Spatial or constructional arrangements of loudspeakers · CPC title

• H03F2200/03

  the amplifier being designed for audio applications · CPC title

• H03F3/187

  in integrated circuits · CPC title

• H04R2430/01

  Aspects of volume control, not necessarily automatic, in sound systems · CPC title

• H04R3/12 Primary

  for distributing signals to two or more loudspeakers {(specially adapted for hearing aids H04R25/407)} · CPC title