Data processing method and data processing apparatus

Patent metadata

Field	Value
Publication number	US-2025392408-A1
Application number	US-202519307910-A
Country	US
Kind code	A1
Filing date	Aug 22, 2025
Priority date	Feb 25, 2023
Publication date	Dec 25, 2025
Grant date	—

Abstract

In an example method, probabilistic constellation shaping (PCS) processing is performed on a first bit set in k bits, to obtain a second bit set. Forward error correction (FEC) encoding is performed on the second bit set and a third bit set in the k bits excluding the first bit set, to obtain a fourth bit set. The fourth bit set includes m0 first bit subsets, and each of the first bit subsets includes F0 bits. First interleaving processing is performed on the fourth bit set to obtain a fifth bit set. The fifth bit set includes m0 second bit subsets, each of the second bit subsets includes F0 bits, F0/2 bits in each of the second bit subsets are from the second bit set, and the other F0/2 bits in each of the second bit subsets are from the third bit set and/or parity bits of the FEC encoding.

First claim

1 . A data processing method, comprising:
performing probabilistic constellation shaping (PCS) processing on a first bit set in k bits, to obtain a second bit set, wherein k is an integer greater than 1; performing forward error correction (FEC) encoding on the second bit set and a third bit set in the k bits excluding the first bit set, to obtain a fourth bit set, wherein the fourth bit set comprises m 0 first bit subsets, each of the first bit subsets comprises F 0 bits, m 0 is an integer greater than 1, and F 0 is an even number greater than 1; and performing first interleaving processing on the fourth bit set to obtain a fifth bit set, wherein the fifth bit set comprises m 0 second bit subsets, each of the second bit subsets comprises F 0 bits,

F
0

2

bits in each of the second bit subsets are form the second bit set, and the other

F
0

2

bits in each of the second bit subsets are from at least one of the third bit set or parity bits of the FEC encoding.

2 . The method according to claim 1 , wherein the fifth bit set comprises m 0 ×F 0 bits, and each of the second bit subsets comprises F 0 consecutive bits.

3 . The method according to claim 1 , wherein each of the second bit subsets is presented as a square block.

4 . The method according to claim 1 , wherein the F 0 bits in each of the second bit subsets are distributed in F 1 rows and F 1 columns,

F
1

2

bits of F 1 bits in each row of each of the second bit subsets are from the second bit set, the second bit set comprises

m
0

×

F
0

2

bits, and the other

F
1

2

bits of the F 1 bits in each row of each of the second bit subsets are from at least one of the third bit set or the parity bits of the FEC encoding.

5 . The method according to claim 4 , wherein F 0 =256 and F 1 =16.

6 . The method according to claim 4 , wherein F 0 =256, F 1 =16, and a bit in row i 2 and column

(

⌊

j
2

2

⌋

×
4

+

j
2

⁢

%
⁢

2

+

i
2

+
2

)

⁢

%
⁢
16

of each of the second bit subsets is form the second bit set, wherein 0≤i 2 <16 and 0≤j 2 <8; or
a bit in row i 2 and column (j 2 ×2−i 2 % 2+1) of each of the second bit subsets is from the second bit set, wherein 0≤i 2 <16 and 0≤j 2 <8, wherein:
└a┘ represents performing a floor operation on a, and b % c represents b modulo c.

7 . The method according to claim 4 , wherein F 0 =256, F 1 =16, and bits in each of the second bit subsets satisfies one or more of the following:
bits in row 0 and columns 2, 3, 6, 7, 10, 11, 14, and 15 of each of the second bit subsets are from the second bit set; bits in row 1 and columns 0, 3, 4, 7, 8, 11, 12, and 15 of each of the second bit subsets are from the second bit set; bits in row 2 and columns 0, 1, 4, 5, 8, 9, 12, and 13 of each of the second bit subsets are from the second bit set; bits in row 3 and columns 1, 2, 5, 6, 9, 10, 13, and 14 of each of the second bit subsets are from the second bit set; bits in row 4 and columns 2, 3, 6, 7, 10, 11, 14, and 15 of each of the second bit subsets are from the second bit set; bits in row 5 and columns 0, 3, 4, 7, 8, 11, 12, and 15 of each of the second bit subsets are from the second bit set; bits in row 6 and columns 0, 1, 4, 5, 8, 9, 12, and 13 of each of the second bit subsets are from the second bit set; bits in row 7 and columns 1, 2, 5, 6, 9, 10, 13, and 14 of each of the second bit subsets are from the second bit set; bits in row 8 and columns 2, 3, 6, 7, 10, 11, 14, and 15 of each of the second bit subsets are from the second bit set; bits in row 9 and columns 0, 3, 4, 7, 8, 11, 12, and 15 of each of the second bit subsets are from the second bit set; bits in row 10 and columns 0, 1, 4, 5, 8, 9, 12, and 13 of each of the second bit subsets are from the second bit set; bits in row 11 and columns 1, 2, 5, 6, 9, 10, 13, and 14 of each of the second bit subsets are from the second bit set; bits in row 12 and columns 2, 3, 6, 7, 10, 11, 14, and 15 of each of the second bit subsets are from the second bit set; bits in row 13 and columns 0, 3, 4, 7, 8, 11, 12, and 15 of each of the second bit subsets are from the second bit set; bits in row 14 and columns 0, 1, 4, 5, 8, 9, 12, and 13 of each of the second bit subsets are from the second bit set; or bits in row 15 and columns 1, 2, 5, 6, 9, 10, 13, and 14 of each of the second bit subsets are from the second bit set.

8 . The method according to claim 1 , wherein F 0 =256, and a total of m 1 ×256 bits in m 1 first bit subsets in the fourth bit set are from the second bit set, wherein m 0 =m 1 ×2.

9 . The method according to claim 1 , wherein F 0 =256, m 0 ×256 bits in the fourth bit set are distributed in 32 rows and m 0 ×8 columns, m 0 ×256 bits in the fifth bit set are distributed in 32 rows and m 0 ×8 columns, and m 0 ×8 bits in row r 1 in the fifth bit set are from m 0 ×8 bits in row r 0 in the fourth bit set, wherein 0≤r 0 <32 and 0≤r 1 <32.

10 . The method according to claim 1 , wherein the performing FEC encoding on the second bit set and a third bit set in the k bits excluding the first bit set, to obtain a fourth bit set comprises:
performing pre-encoding interleaving processing on the second bit set and the third bit set to obtain a sixth bit set, wherein a quantity of bits in the sixth bit set is equal to a sum of a quantity of bits in the second bit set and a quantity of bits in the third bit set, the sixth bit set comprises m 3 third bit subsets, the m 3 third bit subsets are distributed in two rows and m 4 columns, m 3 =2× m 4 , and m 3 is an integer greater than 1 and less than m 0 , wherein some third bit subsets each comprises F 0 bits, the other third bit subsets each comprises F 2 bits, and F 2 is a

Assignees

• Huawei Tech Co Ltd

Inventors

• Huang Kechao
• Luo Ji
• Yang Xiaoling
• Ma Huixiao

Classifications

• H04L1/0071 Primary

  Use of interleaving (interleaving per se H03M13/27) · CPC title

• H03M13/2792

  Interleaver wherein interleaving is performed jointly with another technique such as puncturing, multiplexing or routing · CPC title

• H03M13/2778

  Interleaver using block-wise interleaving, e.g. the interleaving matrix is sub-divided into sub-matrices and the permutation is performed in blocks of sub-matrices · CPC title

• H03M13/29

  combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes · CPC title

• H03M13/09

  Error detection only, e.g. using cyclic redundancy check [CRC] codes or single parity bit · CPC title