Magnetoresistive random access memory device and manufacturing method thereof

Patent metadata

Field	Value
Publication number	US-2025386739-A1
Application number	US-202418747353-A
Country	US
Kind code	A1
Filing date	Jun 18, 2024
Priority date	May 14, 2024
Publication date	Dec 18, 2025
Grant date	—

Abstract

A magnetoresistive random access memory (MRAM) device includes a magnetic tunneling junction (MTJ) structure, a spin-orbit torque (SOT) layer, a first cap layer, an oxide layer, a second cap layer, and a connection structure. The MTJ structure and the SOT layer are disposed above a substrate, and the MTJ structure is located on the SOT layer. The first cap layer is disposed adjacent to the MTJ structure, the oxide layer is disposed on the first cap layer, and the second cap layer is disposed on the oxide layer. The first cap layer, the oxide layer, and the second cap layer are partly disposed above the MTJ structure in a vertical direction. The connection structure is disposed above the MTJ structure and penetrates through the second cap layer, the oxide layer, and the first cap layer vertically.

First claim

What is claimed is:

1 . A magnetoresistive random access memory (MRAM) device, comprising:
a magnetic tunneling junction (MTJ) structure disposed above a substrate; a spin-orbit torque (SOT) layer disposed above the substrate, wherein the MTJ structure is located on the SOT layer; a first cap layer disposed adjacent to the MTJ structure; an oxide layer disposed on the first cap layer; a second cap layer disposed on the oxide layer, wherein the first cap layer, the oxide layer, and the second cap layer are partly disposed above the MTJ structure in a vertical direction; and a connection structure disposed above the MTJ structure and penetrating through the second cap layer, the oxide layer, and the first cap layer vertically.

2 . The MRAM device according to claim 1 , further comprising:
a top electrode disposed on the MTJ structure, wherein the first cap layer, the oxide layer, and the second cap layer are partly located above the top electrode in the vertical direction, and the connection structure penetrates through the second cap layer, the oxide layer, and the first cap layer vertically for contacting the top electrode.

3 . The MRAM device according to claim 2 , wherein a bottom surface of the first cap layer, a bottom surface of the oxide layer, and a bottom surface of the second cap layer are lower than a top surface of the top electrode in the vertical direction.

4 . The MRAM device according to claim 2 , wherein a top surface of the top electrode comprises a curved surface.

5 . The MRAM device according to claim 1 , wherein a sidewall of the oxide layer, a sidewall of the first cap layer, and a sidewall of the SOT layer are aligned with one another.

6 . The MRAM device according to claim 1 , wherein a bottom surface of the second cap layer is lower than a bottom surface of the first cap layer in the vertical direction.

7 . The MRAM device according to claim 1 , wherein the second cap layer is partly disposed on a sidewall of the first cap layer and a sidewall of the SOT layer.

8 . The MRAM device according to claim 1 , wherein a material composition of the oxide layer is different from a material composition of the first cap layer and a material composition of the second cap layer.

9 . The MRAM device according to claim 1 , wherein a material composition of the first cap layer is identical to a material composition of the second cap layer.

10 . The MRAM device according to claim 1 , wherein the oxide layer located above the MTJ structure is sandwiched between the first cap layer and the second cap layer in the vertical direction.

11 . A manufacturing method of a magnetoresistive random access memory (MRAM) device, comprising:
forming a magnetic tunneling junction (MTJ) structure above a substrate; forming a spin-orbit torque (SOT) layer above the substrate, wherein the MTJ structure is located on the SOT layer; forming a first cap layer adjacent to the MTJ structure; forming an oxide layer on the first cap layer; forming a second cap layer on the oxide layer, wherein the first cap layer, the oxide layer, and the second cap layer are partly located above the MTJ structure in a vertical direction; and forming a connection structure above the MTJ structure, wherein the connection structure penetrates through the second cap layer, the oxide layer, and the first cap layer vertically.

12 . The manufacturing method of the MRAM device according to claim 11 , wherein a method of forming the SOT layer comprises:
forming a SOT material above the substrate, wherein the MTJ structure is formed on the SOT material; forming a cap material on the MTJ structure and the SOT material; forming a patterned oxide material on the cap material; and performing an etching process using the patterned oxide material as mask, wherein the SOT material is etched to be the SOT layer by the etching process, and a part of the patterned oxide material is located above the MTJ structure in the vertical direction after the etching process.

13 . The manufacturing method of the MRAM device according to claim 12 , wherein the substrate comprises a memory region and a logic region, the SOT material and the cap material are partly formed above the memory region and partly formed above the logic region, and the SOT material and the cap material located above the logic region are removed by the etching process.

14 . The manufacturing method of the MRAM device according to claim 12 , wherein the cap material is etched to be the first cap layer by the etching process, and the patterned oxide material is etched to be the oxide layer by the etching process.

15 . The manufacturing method of the MRAM device according to claim 12 , further comprising:
forming a top electrode above the substrate before the cap material is formed, wherein the top electrode is located above the MTJ structure, and the cap material covers the top electrode, the MTJ structure, and the SOT material.

16 . The manufacturing method of the MRAM device according to claim 15 , wherein the first cap layer, the oxide layer, and the second cap layer are partly located above the top electrode in the vertical direction, and the connection structure penetrates through the second cap layer, the oxide layer, and the first cap layer vertically for contacting the top electrode.

17 . The manufacturing method of the MRAM device according to claim 15 , wherein a bottom surface of the first cap layer, a bottom surface of the oxide layer, and a bottom surface of the second cap layer are lower than a top surface of the top electrode in the vertical direction.

18 . The manufacturing method of the MRAM device according to claim 15 , wherein a top surface of the top electrode comprises a curved surface.

19 . The manufacturing method of the MRAM device according to claim 12 , wherein the second cap layer is formed after the etching process, and the manufacturing method further comprises:
forming an interlayer dielectric layer on the second cap layer; and performing a planarization process to the interlayer dielectric layer, wherein the planarization process stops on the second cap layer, and a bottom surface of the interlayer dielectric layer is lower than the MTJ structure in the vertical direction.

20 . The manufacturing method of the MRAM device according to claim 19 , wherein a dielectric constant of the interlayer dielectric layer is lower than a dielectric constant of the oxide layer.

Assignees

• United Microelectronics Corp

Inventors

• Wang hui-lin

Classifications

• H10B61/22

  of the field-effect transistor [FET] type · CPC title

• H10N50/01

  Manufacture or treatment · CPC title

• H10N50/85 Primary

  Materials of the active region · CPC title

• H10N50/10 Primary

  Magnetoresistive devices · CPC title