Semiconductor memory device and manufacturing method of semiconductor memory device

Patent metadata

Field	Value
Publication number	US-2025386553-A1
Application number	US-202519304214-A
Country	US
Kind code	A1
Filing date	Aug 19, 2025
Priority date	Apr 5, 2021
Publication date	Dec 18, 2025
Grant date	—

Abstract

A semiconductor memory device includes a channel layer, a gate electrode spaced apart from the channel layer, a blocking insulating layer between the gate electrode and the channel layer, a tunnel insulating layer between the channel layer and the blocking insulating layer, and nano-particles spaced apart from each other between the tunnel insulating layer and the blocking insulating layer.

First claim

What is claimed is:

1 . A method of manufacturing a semiconductor memory device, the method comprising:
forming a stack structure including first material layers and second material layers, which are alternately stacked; forming a hole penetrating the stack structure; forming a recess region between the first material layers by etching a portion of each of the second material layers through the hole; forming a blocking insulating layer on a sidewall of the hole, wherein the blocking insulating layer is formed to have an uneven surface along surfaces of the recess region and the hole; forming a data storage layer having nano-particles spaced apart from each other on the blocking insulating layer, wherein the data storage layer is disposed in a groove of the blocking insulating layer defined at each level where the second material layers are disposed; forming a tunnel insulating layer on the data storage layer; aggregating the nano-particles; and forming a channel layer on the tunnel insulating layer.

2 . The method of claim 1 ,
wherein the tunnel insulating layer is in contact with the blocking insulating layer at each level where the first material layers are disposed.

3 . The method of claim 1 , wherein the forming the data storage layer comprises:
forming a Metal Organic Framework (MOF) on the blocking insulating layer; infiltrating a metal precursor into pores of the MOF; and growing the nano-particles in the pores.

4 . The method of claim 3 , further comprising removing an organic ligand of the MOF after growing the nano-particles.

5 . The method of claim 1 , wherein the forming the data storage layer includes:
forming the nano-particles on the blocking insulating layer; and adjusting a distance between the nano-particles by adsorbing a Self-Assembled Monolayer (SAM) on the nano-particles.

6 . The method of claim 5 , further comprising removing the SAM after adjusting the distance between the nano-particles.

7 . A method of manufacturing a semiconductor memory device, the method comprising:
forming a stack structure including first material layers and second material layers, which are alternately stacked; forming a hole penetrating the stack structure; forming a recess region between the first material layers by etching a portion of each of the second material layers through the hole; forming a blocking insulating layer on a sidewall of the hole, wherein the blocking insulating layer is formed to have an uneven surface along surfaces of the recess region and the hole; forming a data storage layer having nano-particles spaced apart from each other on the blocking insulating layer, wherein the data storage layer is disposed in a groove of the blocking insulating layer defined at each level where each of the second material layers is disposed; forming a tunnel insulating layer on the data storage layer; and forming a channel layer on the tunnel insulating layer, wherein the forming the data storage layer comprises: forming a Metal Organic Framework (MOF) on the blocking insulating layer; infiltrating a metal precursor into pores of the MOF; and growing the nano-particles in the pores; removing an organic ligand of the MOF after growing the nano-particles; and aggregating the nano-particles in the recess region.

8 . The method of claim 7 , wherein the tunnel insulating layer is in contact with the blocking insulating layer at each level where each of the first material layers is disposed.

9 . A method of manufacturing a semiconductor memory device, the method comprising:
forming a stack structure including first material layers and second material layers, which are alternately stacked; forming a hole penetrating the stack structure; forming a recess region between the first material layers by etching a portion of each of the second material layers through the hole; forming a blocking insulating layer on a sidewall of the hole, wherein the blocking insulating layer is formed to have an uneven surface along surfaces of the recess region and the hole; forming a data storage layer having nano-particles spaced apart from each other on the blocking insulating layer, wherein the data storage layer is disposed in a groove of the blocking insulating layer defined at each level where each of the second material layers is disposed; forming a tunnel insulating layer on the data storage layer; and forming a channel layer on the tunnel insulating layer, wherein the forming the data storage layer comprises: forming the nano-particles on the blocking insulating layer; and adjusting a distance between the nano-particles by adsorbing a Self-Assembled Monolayer (SAM) on the nano-particles; removing the SAM after adjusting the distance between the nano-particles; and aggregating the nano-particles in the recess region.

10 . The method of claim 9 , wherein the tunnel insulating layer is in contact with the blocking insulating layer at each level where each of the first material layers is disposed.

Assignees

• Sk Hynix Inc

Inventors

• Han Jae Hyun
• Koo Won Tae

Classifications

• H10D64/037

  comprising charge-trapping insulators · CPC title

• H10D64/035 Primary

  comprising conductor-insulator-conductor-insulator-semiconductor structures · CPC title

• H10D30/697

  having trapping at multiple separated sites, e.g. multi-particles trapping sites · CPC title

• H10B43/27

  the channels comprising vertical portions, e.g. U-shaped channels · CPC title

• H10B41/27

  the channels comprising vertical portions, e.g. U-shaped channels · CPC title