Hybrid and adaptive offset calibration for sar adc

Patent metadata

Field	Value
Publication number	US-2025385685-A1
Application number	US-202418745693-A
Country	US
Kind code	A1
Filing date	Jun 17, 2024
Priority date	Jun 17, 2024
Publication date	Dec 18, 2025
Grant date	—

Abstract

A SAR ADC is provided with a hybrid offset calibration that includes a digital calibration without bit extension. Due to the lack of bit extension, the digital calibration can only address integer multiples of least-significant bits for the offset. The hybrid offset calibration further includes an analog calibration that addresses a remaining fraction of a least-significant bit of the offset.

First claim

What is claimed is:

1 . A successive-approximation-register (SAR) analog-to-digital converter (ADC) system, comprising:
a SAR ADC configured to convert an analog input signal into an uncorrected digital output signal, the SAR ADC including an analog calibration circuit responsive to an analog correction code; a digital adder configured to add a digital calibration code to the uncorrected digital output signal to produce a corrected digital output signal; and a controller configured to adjust the digital calibration code and the analog calibration code responsive to a DC offset in the uncorrected digital output signal.

2 . The successive-approximation-register (SAR) analog-to-digital converter (ADC) system of claim 1 , wherein the controller is further configured to adjust the analog calibration code to not exceed an upper limit and to not be less than a lower limit.

3 . The successive-approximation-register (SAR) analog-to-digital converter (ADC) system of claim 2 , wherein analog calibration circuit is configured to produce an offset in the uncorrected digital output signal equaling a difference between one half of a least-significant bit (0.5 LSB) and a desired limit (Vtarget) for a residue offset of the corrected digital output signal in response to the analog calibration code equaling the upper limit, and wherein the analog calibration circuit is further configured to produce an offset in the uncorrected digital output signal equaling −(0.5 LSB−Vtarget) in response to the analog calibration code equaling the lower limit.

4 . The successive-approximation-register (SAR) analog-to-digital converter (ADC) system of claim 3 , wherein the controller is further configured to adjust the upper limit and the lower limit responsive to the residue offset of the corrected digital output signal.

5 . The successive-approximation-register (SAR) analog-to-digital converter (ADC) system of claim 4 , wherein the controller is further configured to adjust the upper limit and the lower limit responsive to an absolute value of the residue offset exceeding Vtarget.

6 . The successive-approximation-register (SAR) analog-to-digital converter (ADC) system of claim 3 , wherein the controller is further configured to respond to the residue offset exceeding Vtarget while the analog calibration code equals the upper limit by switching the analog calibration code to equal the lower limit.

7 . The successive-approximation-register (SAR) analog-to-digital converter (ADC) system of claim 6 , wherein the controller is further configured to increment or decrement the digital calibration code by one LSB in response to the switching of the analog calibration code.

8 . The successive-approximation-register (SAR) analog-to-digital converter (ADC) system of claim 7 , wherein the SAR ADC is further configured to assert a timing bit in response to a change in the uncorrected digital output signal from the switching of the analog calibration code, and wherein the controller is further configured to increment or decrement the digital calibration code only after an assertion of the timing bit.

9 . The successive-approximation-register (SAR) analog-to-digital converter (ADC) system of claim 3 , wherein the controller is further configured to respond to the residue offset being less than −Vtarget while the analog calibration code equals the lower limit by switching the analog calibration code to equal the upper limit.

10 . The successive-approximation-register (SAR) analog-to-digital converter (ADC) system of claim 9 , wherein the SAR ADC is further configured to assert a timing bit in response to a change in the uncorrected digital output signal from the switching of the analog calibration code, and wherein the controller is further configured to increment or decrement the digital calibration code in response to an assertion of the timing bit.

11 . The successive-approximation-register (SAR) analog-to-digital converter (ADC) system of claim 10 , wherein the controller is further configured to increment or decrement the digital calibration code by only one LSB.

12 . The successive-approximation-register (SAR) analog-to-digital converter (ADC) system of claim 1 , wherein the SAR ADC includes a comparator, and wherein the analog calibration circuit comprises at least one first variable capacitor coupled to a first output terminal of the comparator and comprises at least one second variable capacitor coupled to a second output terminal of the comparator.

13 . A method of calibrating a DC offset of an uncorrected digital output signal of a SAR ADC, comprising:
adding a digital calibration code to the uncorrected digital output signal responsive to the DC offset of the uncorrected digital output signal to form a corrected digital output signal, wherein the digital calibration code equals an integer multiple of a least-significant bit (LSB) of the DC offset; and adjusting an analog calibration circuit in the SAR ADC to substantially eliminate a remaining fraction of the LSB of the DC offset.

14 . The method of claim 13 , wherein adjusting the analog calibration circuit is responsive to an analog calibration code, the method further comprising:
generating an analog calibration code to not exceed an upper limit and to not be less than a lower limit.

15 . A serializer-deserializer receiver, comprising:
a continuous-time linear equalizer configured to process an input signal to produce a plurality of analog-to-digital converter (ADC) input signals; a plurality of ADC slices corresponding to the plurality of ADC input signals, each ADC slice including a successive-approximation register (SAR) ADC system configured to digitize a corresponding one of the ADC input signals, wherein each SAR ADC system comprises: a SAR ADC configured to convert an analog input signal into an uncorrected digital output signal having a DC offset, the SAR ADC including an analog calibration circuit responsive to an analog correction code; a digital adder configured to add a digital calibration code to the uncorrected digital output signal to produce a corrected digital output signal; and a controller configured to generate the digital calibration code and to generate the analog calibration code responsive to the DC offset.

16 . The serializer-deserializer receiver of claim 15 , wherein the serializer-deserializer receiver comprise a pulse amplitude modulation 4-level (PAM4) serializer-deserializer receiver.

17 . The serializer-deserializer receiver of claim 15 , wherein the controller is further configured to generate the digital calibration code without bit extension, and wherein the serializer-deserializer receiver is incorporated into a processor.

18 . The serializer-deserializer receiver of claim 15 , further comprising:
a data combiner configured to combine the corrected digital output signal from each ADC slice to form an ADC digital output signal; a digital signal processor configured to digitally equalize the ADC digital output signal to produce a serializer-deserializer output signal; and a clock-data recovery circuit configured to extract a clock signal from the ADC digital output signal.

19 . The serializer-deserializer receiver of claim 15 , wherein each controller is further configured to adjust its analog calibration code to be within an upper limit and a lower limit.

20 . The serializer-deserializer receiver of claim 19 , wherein each analog calibration circuit is configured to produce an offset in its ADC slice's uncorrected digital ou

Assignees

• Qualcomm Inc

Inventors

• Tang Yongjian
• Arcudia Kenneth Luis

Classifications

• H03M1/1023 Primary

  Offset correction (H03M1/1019 takes precedence; removal of offset already present on the analogue input signal H03M1/1295) · CPC title

• H03M1/1038

  by storing corrected or correction values in one or more digital look-up tables (H03M1/1057 takes precedence) · CPC title

• H03M1/46

  with digital/analogue converter for supplying reference values to converter · CPC title

• H03M1/462 Primary

  Details of the control circuitry, e.g. of the successive approximation register · CPC title