Apparatus and method of making and using multi-conductor cables on flexible silicon cables with resistive and superconducting applications

US2025385454A1 · US · A1

Patent metadata
FieldValue
Publication numberUS-2025385454-A1
Application numberUS-202519239343-A
CountryUS
Kind codeA1
Filing dateJun 16, 2025
Priority dateJun 14, 2024
Publication dateDec 18, 2025
Grant date

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A method to create flexible mutli-conductor cables include fabricating wiring on silicon-on-insulator wafers with lithographic fabrication techniques followed by thinning some sections of the wafer with a silicon etch. Exemplary cables can have fine pitch and low thermal conductivity enabling high density superconducting interconnects between different temperature stages in cryogenic platforms or between superconducting circuits oriented perpendicular to each other. Also presented herein are methods for making and using exemplary cables.

First claim

Opening claim text (preview).

What is claimed is: 1 . A method of fabricating a flexible circuitry device using semiconductor processing, the method comprising the steps of: fabricating wiring and/or circuitry on a device layer of a silicon-on-insulator wafer having a thick, relative to other layers of the flexible circuitry device, silicon handle layer, a buried oxide layer, and the device layer; etching a pattern in the device and buried oxide layers; and removing a portion of the handle layer from the wafer using a backside deep silicone etch, thereby leaving an area having only the device layer plus the added wiring and/or circuitry and is thereby flexible at that relatively thin silicon layer. 2 . The method of claim 1 , wherein the silicon device layer is 1-20 microns thick. 3 . The method of claim 1 , wherein the silicon device layer is under 4 microns thick. 4 . The method of claim 1 , wherein the device layer is a semiconductor grade monocrystalline Silicon layer. 5 . The method of claim 1 , wherein the backside deep silicone etch is a backside silicon deep reactive ion etch. 6 . The method of claim 1 , further comprising the step of: removing the buried oxide layer. 7 . A flexible circuitry device manufactured by semiconductor processing comprising: a first rigid semiconductor portion having a silicon device layer and a handle layer, the handle layer of the first portion being thick relative to the device layer of the first portion; a second rigid semiconductor portion having a silicon device layer and a handle layer, the handle layer of the second portion being thick relative to the device layer of the second portion; and a flexible portion connecting the first rigid portion and the second rigid portion, the flexible portion having wiring electrically connecting a portion of the first rigid portion to the second rigid portion. 8 . The flexible circuitry device of claim 7 , wherein the wiring is resistive wiring. 9 . The flexible circuitry device of claim 7 , wherein the wiring is superconducting wiring. 10 . The flexible circuitry device of claim 7 , wherein the first rigid portion includes circuit elements fabricated on the device layer of the first rigid portion. 11 . The flexible circuitry device of claim 7 , wherein the flexible portion is monolithic with the device layers of the first and second rigid portions. 12 . A method of using a flexible circuitry device having a flexible portion, the method comprising the steps of: mounting the flexible circuitry device on a sample box of a jigging assembly using alignment features of the sample box tending to accept and cradle the flexible circuitry device when being mounted on the sample box; bending the flexible circuitry device at the flexible portion using a bender of the jigging assembly, the bender guided by a guide of the jigging assembly; and removing the flexible circuitry device from the jigging. 13 . The method of claim 12 , wherein the guide includes slots configured to accept rails of the bender. 14 . The method of claim 12 , wherein the flexible circuitry device is bent approximately 90 degrees. 15 . The method of claim 12 , wherein during bending, the flexible portion is protected by the jigging assembly and not touched by any portions of the jigging assembly. 16 . The method of claim 15 , further comprising the step of: the bender remaining in place while mechanical fasteners are inserted through holes in the bender. 17 . The method of claim 16 wherein, during insertion of the mechanical fasteners the flexible portion is protected from accidental contact by a mechanical cover. 18 . The method of claim 12 , further comprising the step of: the bender remaining in place while mechanical fasteners are inserted through holes in the bender. 19 . The method of claim 12 , further comprising the steps of: removing the bender from the flexible circuitry device; and affixing a cover to the flexible circuitry device covering the flexible portion. 20 . The method of claim 12 , further comprising the step of: installing a final cover on the flexible circuitry device after removal from the jigging.

Assignees

Inventors

Classifications

  • for manufacturing contact members, e.g. by punching and by bending · CPC title

  • H01R12/79Primary

    connecting to rigid printed circuits or like structures · CPC title

  • H10N60/01Primary

    Manufacture or treatment · CPC title

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Frequently asked questions

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What does patent US2025385454A1 cover?
A method to create flexible mutli-conductor cables include fabricating wiring on silicon-on-insulator wafers with lithographic fabrication techniques followed by thinning some sections of the wafer with a silicon etch. Exemplary cables can have fine pitch and low thermal conductivity enabling high density superconducting interconnects between different temperature stages in cryogenic platforms …
Who is the assignee on this patent?
Government Of The Us Secretary Of Commerce
What technology area does this patent fall under?
Primary CPC classification H01R12/79. Mapped technology areas include Electricity.
When was this patent published?
Publication date Thu Dec 18 2025 00:00:00 GMT+0000 (Coordinated Universal Time) (A1). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).