Display substrate, display panel and display device

Patent metadata

Field	Value
Publication number	US-2025384845-A1
Application number	US-202519303517-A
Country	US
Kind code	A1
Filing date	Aug 19, 2025
Priority date	May 27, 2022
Publication date	Dec 18, 2025
Grant date	—

Abstract

A display substrate includes: a base substrate; light-emitting elements located in a display area; pixel driving circuits located respectively connected to the light-emitting elements, each pixel driving circuit including an N-type transistor and a P-type transistor; a first gate driving circuit, a second gate driving circuit and a third gate driving circuit in a border area of the display area, the first and third gate driving circuits being connected with the P-type transistor, the second gate driving circuit being connected with the N-type transistor, and orthographic projections of the first to third gate driving circuits on the base substrate are not overlapped with each other; and a planarization layer located between the pixel driving circuits and the light-emitting elements.

First claim

What is claimed is:

1 . A display substrate, comprising:
a base substrate; a plurality of light-emitting elements located in a display area; a plurality of pixel driving circuits located on the base substrate, at least one of the pixel driving circuits comprises an N-type transistor and a P-type transistor; a first gate driving circuit, a second gate driving circuit and a third gate driving circuit each located on the base substrate and at least arranged in a border area at a periphery of the display area; the third gate driving circuit, the second gate driving circuit and the first gate driving circuit are sequentially arranged along a direction away from the display area, and orthographic projections of the third gate driving circuit, the second gate driving circuit and the first gate driving circuit on the base substrate are not overlapped with each other; wherein orthographic projections of adjacent boundary areas of the first gate driving circuit and the second gate driving circuit on the base substrate are at least partially nested.

2 . The display substrate of claim 1 , wherein a part of a boundary area of the first gate driving circuit adjacent to the second gate driving circuit is formed with a first notch portion; a part of a boundary area of the second gate driving circuit, which is close to the first gate driving circuit, extends to a region where the first gate driving circuit is located to form a first protruding portion;
the first protruding portion is correspondingly located in the first notch portion, and a shape of an orthographic projection of the first protruding portion on the base substrate is matched with a shape of an orthographic projection of the first notch portion on the base substrate.

3 . The display substrate of claim 1 , wherein a part of a boundary area of the second gate driving circuit close to the first gate driving circuit is formed with a second notch portion; a part of a boundary area of the first gate driving circuit close to the second gate driving circuit extends to a region where the second gate driving circuit is located to form a second protruding portion;
the second protruding portion is correspondingly located in the second notch portion, and a shape of an orthographic projection of the second protruding portion on the base substrate is matched with a shape of an orthographic projection of the second notch portion on the base substrate.

4 . The display substrate of claim 2 , further comprising: a first semiconductor layer and a first conductive layer sequentially stacked on the base substrate, and a gate insulating layer is arranged between the first semiconductor layer and the first conductive layer, wherein
the first gate driving circuit and the second gate driving circuit each comprise a plurality of transistors; the first semiconductor layer comprises patterns of active layers of the transistors; the patterns of part of the active layers in the first semiconductor layer are located in the first protruding portion.

5 . The display substrate of claim 2 , further comprising: a first semiconductor layer and a first conductive layer sequentially stacked on the base substrate, and a gate insulating layer is arranged between the first semiconductor layer and the first conductive layer, wherein
the first gate driving circuit and the second gate driving circuit each comprise a plurality of capacitors; the first conductive layer comprises patterns of gates of the transistors, first connection lines connected to the gates, first plates of the capacitors and second connection lines connected to the first plates; the patterns of part of the gates in the first conductive layer are located in the first protruding portion.

6 . The display substrate of claim 5 , further comprising a second conductive layer located on a side of the first conductive layer away from the base substrate, and a first passivation layer is arranged between the second conductive layer and the first conductive layer;
the second conductive layer comprises patterns of second plates of the capacitors and third connection lines; the second plates of part of the capacitors in the second conductive layer are located in the first protruding portion.

7 . The display substrate of claim 6 , further comprising a third conductive layer on a side of the second conductive layer away from the base substrate, wherein a second passivation layer is arranged between the third conductive layer and the second conductive layer;
the third conductive layer comprises patterns of fifth connection lines.

8 . The display substrate of claim 7 , further comprising a fourth conductive layer locate on a side of the third conductive layer away from the base substrate, wherein
a first intermediate dielectric layer and a second intermediate dielectric layer are arranged between the fourth conductive layer and the third conductive layer, and the first intermediate dielectric layer and the second intermediate dielectric layer are stacked sequentially in a direction away from the third conductive layer; first layer via holes are formed in the first intermediate dielectric layer and configured to connect conductive patterns in the fourth conductive layer to conductive patterns in the third conductive layer; second layer via holes are formed in the second intermediate dielectric layer and are configured to connect the conductive patterns in the fourth conductive layer to conductive patterns in the first conductive layer and conductive patterns in the second conductive layer, respectively; the fourth conductive layer comprises patterns of sources and drains of the transistors and sixth connection lines; the sixth connection lines are configured to be connected to the sources, the drains and the gates; the patterns of part of the sources or part of the drains in the fourth conductive layer are located in the first protruding portion.

9 . The display substrate of claim 1 , wherein the first gate driving circuit and the third gate driving circuit are connected with the P-type transistor in the at least one of the pixel driving circuits, the second gate driving circuit is connected to the N-type transistor in the at least one of the pixel driving circuits.

10 . The display substrate of claim 1 , further comprising a planarization layer located between the pixel driving circuits and the light-emitting elements and extending to be of an entire surface structure to cover the first gate driving circuit, the second gate driving circuit and the third gate driving circuit.

11 . The display substrate of claim 1 , further comprising:
a first group of signal lines connected to the first gate driving circuit; a second group of signal lines connected to the second gate driving circuit; a third group of signal lines connected to the third gate driving circuit, wherein orthographic projections of the first group of signal lines on the base substrate are overlapped with the orthographic projection of the first gate driving circuit on the base substrate; orthographic projections of the second group of signal lines on the base substrate are overlapped with the orthographic projection of the second gate driving circuit on the base substrate; and orthographic projections of the third group of signal lines on the base substrate are overlapped with the orthographic projection of the third gate driving circuit on the base substrate.

12 . The display substrate of claim 11 , wherein the first group of signal lines, the second group of signal lines, and the third group of signal lines each comprise a power signal line and a clock signal line,
the power signal line comprises a first pow

Assignees

• Chengdu Boe Optoelect Tech Co
• Boe Technology Group Co Ltd

Inventors

• Fan Cong
• Dong Xiangdan
• Tong Kemeng
• Ma Hongwei
• Wang Rong

Classifications

• G11C19/287

  Organisation of a multiplicity of shift registers · CPC title

• G09G2310/0286

  Details of a shift registers arranged for use in a driving circuit · CPC title

• G09G2310/0267

  Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays · CPC title

• G09G2310/0232

  Special driving of display border areas · CPC title

• G09G2300/0842

  forming a memory circuit, e.g. a dynamic memory with one capacitor · CPC title