Electronic device and method for scheduling threads

Patent metadata

Field	Value
Publication number	US-2025383932-A1
Application number	US-202519189380-A
Country	US
Kind code	A1
Filing date	Apr 25, 2025
Priority date	Jun 12, 2024
Publication date	Dec 18, 2025
Grant date	—

Abstract

An electronic device is provided. The electronic device includes a memory storing a program instruction and a central processing unit (CPU) with a first core and a second core. The computing power of the first core is higher than the computing power of the second core. The CPU is configured to read and execute the program instruction to implement a scheduler, a policy hint module, and an application. The CPU is further configured to calculate the required computing power of a thread of the application. When the required computing power of the thread is higher than a threshold, the policy hint module is configured to transmit a message to the scheduler, and the message indicates that the thread has to be allocated to the first core.

First claim

What is claimed is:

1 . An electronic device, comprising:
a memory, storing a program instruction; a central processing unit (CPU), comprising a first core and a second core, wherein a computing power of the first core is higher than a computing power of the second core; wherein the CPU is configured to read and execute the program instruction to implement a scheduler, a policy hint module, and an application; wherein the CPU is configured to calculate a required computing power of a first thread of the application; wherein when the required computing power of the first thread is higher than a first threshold, the policy hint module is configured to transmit a message to the scheduler, and the message indicates that the first thread has to be allocated to the first core.

2 . The electronic device as claimed in claim 1 , wherein when the required computing power of the first thread is lower than the first threshold, the policy hint module is configured not to transmit the message to the scheduler.

3 . The electronic device as claimed in claim 1 , wherein when the required computing power of the first thread is higher than the first threshold and the first core is under a high load, the policy hint module is configured to transmit the message to the scheduler, and the message indicates that the first thread has to be allocated to the second core.

4 . The electronic device as claimed in claim 1 , wherein the CPU further comprises a third core, and a computing power of the third core is lower than the computing power of the second core;
wherein when the required computing power of the first thread is lower than the first threshold and higher than a second threshold, the policy hint module is configured to transmit the message to the scheduler, and the message indicates that the first thread has to be allocated to the first core or the second core; wherein when the required computing power of the first thread is lower than the second threshold, the policy hint module is configured not to transmit the message to the scheduler.

5 . The electronic device as claimed in claim 4 , when the required computing power of the first thread is lower than the first threshold and higher than a second threshold and the first core is under a high load, the policy hint module is configured to transmit the message to the scheduler, and the message indicates that the first thread has to be allocated to the second core.

6 . The electronic device as claimed in claim 1 , wherein the CPU is configured to calculate the required computing power of the first thread based on a time duration it previously took the CPU to execute the first thread, the previous power consumption, temperature, and frequency of the CPU when the CPU was executing the first thread, and a latency requirement of the first thread.

7 . The electronic device as claimed in claim 1 , wherein after the first thread has been allocated to one of the first core and the second core, the CPU is further configured to:
determine a priority of the first thread is higher than a priority of a second thread which is being executed on the one of the first core and the second core; and execute the first thread on the one of the first core and the second core and stop executing the second thread.

8 . The electronic device as claimed in claim 7 , wherein the threads with latency requirements have higher priority than the threads that do not have latency requirements.

9 . A method for scheduling threads, executed by an electronic device comprising a central processing unit (CPU) and a memory storing a program instruction, wherein the CPU comprises a first core and a second core, and a computing power of the first core is higher than a computing power of the second core, wherein the CPU is configured to read and execute the program instruction to implement a scheduler, a policy hint module, and an application, wherein the method comprises:
calculating, via the CPU, a required computing power of a first thread of the application; transmitting, via the policy hint module, a message to the scheduler, when the required computing power of the first thread is higher than a first threshold, wherein the message indicates that the first thread has to be allocated to the first core.

10 . The method as claimed in claim 9 , further comprising:
not transmitting, via the policy hint module, the message to the scheduler, when the required computing power of the first thread is lower than the first threshold.

11 . The method as claimed in claim 9 , further comprising:
transmitting, via the policy hint module, the message to the scheduler, when the required computing power of the first thread is higher than the first threshold and the first core is under a high load, wherein the message indicates that the first thread has to be allocated to the second core.

12 . The method as claimed in claim 9 , wherein the CPU further comprises a third core, and a computing power of the third core is lower than the computing power of the second core, wherein the method further comprises:
transmitting, via the policy hint module, the message to the scheduler, when the required computing power of the first thread is lower than the first threshold and higher than a second threshold, wherein the message indicates that the first thread has to be allocated to the first core or the second core; not transmitting, via the policy hint module, the message to the scheduler, when the required computing power of the first thread is lower than the second threshold.

13 . The method as claimed in claim 12 , further comprising:
transmitting, via the policy hint module, the message to the scheduler, when the required computing power of the first thread is lower than the first threshold and higher than a second threshold and the first core is under a high load, wherein the message indicates that the first thread has to be allocated to the second core.

14 . The method as claimed in claim 9 , further comprising:
calculating, via the CPU, the required computing power of the first thread based on based on a time duration it previously took the CPU to execute the first thread, the previous power consumption, temperature, and frequency of the CPU when the CPU was executing the first thread, and a latency requirement of the first thread.

15 . The method as claimed in claim 9 , wherein after the first thread has been allocated to one of the first core and the second core, the method further comprises:
determining, via the CPU, a priority of the first thread is higher than a priority of a second thread which is being executed on the one of the first core and the second core; and executing, via the CPU, the first thread on the one of the first core and the second core and stop executing the second thread.

16 . The method as claimed in claim 15 , wherein the threads with latency requirements have higher priority than the threads that do not have latency requirements.

Assignees

• Mediatek Inc

Inventors

• Wang Chuang-Yin
• Ho Chung-Hao
• Lee Hao-Kai
• Tsai Tsung-Yu
• Tsai Cheng-Han
• Chen Cheng-Che

Classifications

• G06F2209/5022

  Workload threshold · CPC title

• G06F9/505 Primary

  considering the load · CPC title

• G06F9/5044 Primary

  considering hardware capabilities · CPC title

• G06F2209/5018

  Thread allocation · CPC title