Device and method for bit-stream generation for stochastic computing applications

Patent metadata

Field	Value
Publication number	US-2025383841-A1
Application number	US-202519238245-A
Country	US
Kind code	A1
Filing date	Jun 13, 2025
Priority date	Jun 13, 2024
Publication date	Dec 18, 2025
Grant date	—

Abstract

A cost-effective and highly efficient bit-stream generator for stochastic computing division circuits implementing powers-of-2 Van der Corput (VDC) sequences for bit-stream generation, providing high accuracy operation and low-cost implementation. The correlator design provides high-quality input bit-streams for all stochastic computing division designs, wherein a single random number generator is shared among the input bit-streams of the stochastic computing divider circuit.

First claim

We claim:

1 . A circuit device for performing division operations in a stochastic computing device comprising:
at least two inputs; at least one bit-stream generator, comprising:
a random number generator; and
a comparator;
a down counter; an AND gate; a divider; and electronic circuitry connecting the circuit components;
wherein the bit-stream generator determines the random number generator for one input;
wherein one other input correlates the first generated bit stream through the down counter;
wherein one input is an input for the bit-stream generator;
wherein other input is an input for the down counter;
wherein an output of the bit-stream generator and an output of the down counter are inputs for the AND gate;
wherein the output of bit-stream generator comprises a divisor;
wherein the output of the AND gate comprises a dividend; and
wherein the divisor and the dividend are inputs for the divider.

2 . The device of claim 1 wherein the divider comprises functionality to perform correlated division.

3 . The device of claim 1 wherein the divider comprises functionality to perform saturating subtractor division.

4 . The device of claim 1 wherein the divider comprises functionality to perform min-max-based stochastic division.

5 . A method for performing division operations in a stochastic computing device comprising:
a. providing a circuit device comprising:
at least two inputs, comprising X and Y;
at least one bit-stream generator, comprising:
a random number generator; and
a comparator;

a down counter;
an AND gate;
a divider; and
electronic circuitry connecting the circuit components;
b. inputting one input to one bit stream generator; c. initializing a low discrepancy sequence by one bit stream generator to create a Y bit-stream; d. creating a correlated bit-stream, comprising an X bit-stream, by one bit stream generator, the down counter, and the AND gate; e. inputting the Y bit-stream and X bit-stream to the divider; f. dividing the X bit-stream by the Y bit-stream by the divider; and g. outputting a result.

6 . The method of claim 5 wherein data received from the at least two inputs is in binary format.

7 . The method of claim 5 wherein the division step performed by the divider comprises correlated division.

8 . The method of claim 5 wherein the division step performed by the divider comprises saturating subtractor division.

9 . The method of claim 5 wherein the division step performed by the divider comprises min-max-based stochastic division.

10 . The method of claim 5 , wherein the step to create the correlated bit-stream comprises:
a. the down counter counts each clock cycle; b. one bit stream generator duplicates the Y-bit stream for each bit, comprising if

Y
-
1

N

>

LD_seq
⁢

(
i
)

,

 then the bit equals 1;
wherein N represents a bit-stream size;
and i represents a placement of a bit within a bit-stream, such that i=1 to N;

c. repeating steps a and b above until the clock cycle equals zero; and
d. setting all remaining bits to zero by a zero port.

Assignees

• Univ Louisiana At Lafayette

Inventors

• Najafi Mohammadhassan
• Moghadam Mehran Shoushtari
• Aygun Sercan
• Asadi Sina

Classifications

• G06F7/535 Primary

  Dividing only · CPC title