Memory controller, memory system including the same and operating method thereof

Patent metadata

Field	Value
Publication number	US-2025383790-A1
Application number	US-202418987084-A
Country	US
Kind code	A1
Filing date	Dec 19, 2024
Priority date	Jun 14, 2024
Publication date	Dec 18, 2025
Grant date	—

Abstract

Provided is a memory controller including an interface including a plurality of pins configured to communicate with a memory apparatus, a queue manager configured to control a first queue to store control information for controlling an operation of the memory apparatus storing or reading data and a second queue to store data transmission information for controlling transmission of the data, and an interface controller configured to shut off power to at least one pin among the plurality of pins based on the first queue and the second queue.

First claim

What is claimed is:

1 . A memory controller comprising:
an interface including a plurality of pins configured to communicate with a memory apparatus; a queue manager configured to control a first queue to store control information for controlling an operation of the memory apparatus storing or reading data, and a second queue to store data transmission information for controlling transmission of the data; and an interface controller configured to shut off power to at least one pin among the plurality of pins based on the first queue and the second queue.

2 . The memory controller of claim 1 , wherein the plurality of pins includes a command pin configured to transmit the control information to the memory apparatus and a data pin configured to transmit the data to the memory apparatus according to the data transmission information or receive the data from the memory apparatus.

3 . The memory controller of claim 2 , wherein the interface controller is configured to:
when the first queue is in an empty state, shut off power to the command pin, and
when the second queue is in an empty state, shut off power to the data pin.

4 . The memory controller of claim 2 ,
wherein the plurality of pins further includes a reference voltage pin configured to provide a reference voltage for identifying a state of a signal, and
wherein the interface controller is configured to, when the first queue and the second queue are each in an empty state, shut off power to the reference voltage pin.

5 . The memory controller of claim 2 , wherein the control information includes at least one of a command for controlling an operation of the memory apparatus and an address indicating a storage area of the memory apparatus.

6 . The memory controller of claim 2 , wherein the plurality of pins further includes a read enable pin configured to transmit a read enable signal for controlling an output of the data to the memory apparatus.

7 . The memory controller of claim 6 , wherein the interface controller is configured to, when the second queue is in an empty state, shut off power to the data pin and the read enable pin.

8 . The memory controller of claim 6 , wherein the interface controller is configured to shut off power to the read enable pin based on a type of data indicated by the data transmission information stored in the second queue.

9 . The memory controller of claim 8 , wherein the interface controller is configured to:
when the data is write data, shut off power to the read enable pin while transmitting the write data through the data pin, and
when the data is read data, maintain power to the read enable pin while receiving the read data through the data pin.

10 . The memory controller of claim 1 , wherein the interface controller is configured to shut off power to each of the plurality of pins according to a power-down signal received from outside.

11 . An operating method of a memory controller including a plurality of pins configured to communicate with a memory apparatus, the operating method comprising:
identifying a first queue for storing control information for controlling an operation of the memory apparatus storing or reading data and a second queue for storing data transmission information for controlling transmission of the data; and shutting off power to at least one pin among the plurality of pins based on the first queue and the second queue.

12 . The operating method of claim 11 , wherein the shutting off power to at least one pin includes:
when the first queue is in an empty state, shutting off power to a command pin configured to transmit the control information among the plurality of pins; and when the second queue is in an empty state, shutting off power to a data pin configured to transmit and receive the data among the plurality of pins.

13 . The operating method of claim 12 , wherein the shutting off the power to the data pin includes, when the second queue is in the empty state, shutting off the power to the data pin and a read enable pin together among the plurality of pins.

14 . The operating method of claim 11 , wherein the shutting off the power to at least one pin further includes, when the first queue and the second queue are in an empty state, shutting off power to a reference voltage pin configured to provide a reference voltage to the memory apparatus among the plurality of pins.

15 . The operating method of claim 11 , wherein the shutting off the power to at least one pin includes determining whether to shut off power to a read enable pin among the plurality of pins based on a type of data indicated by the data transmission information stored in the second queue.

16 . The operating method of claim 15 , wherein the determining whether to shut off the power to the read enable pin includes:
when the type of the data is write data, shutting off power to the read enable pin while transmitting the write data through a data pin; and when the type of the data is read data, maintaining power to the read enable pin while receiving the read data through the data pin.

17 . The operating method of claim 11 , further comprising shutting off power to each of the plurality of pins when a power-down signal is received from outside.

18 . A memory system comprising:
a memory apparatus configured to store data; and a memory controller configured to identify a first queue for storing control information for controlling an operation of the memory apparatus storing or reading the data and a second queue for storing data transmission information for controlling transmission of the data and to shut off power to at least one pin among a plurality of pins based on the first queue and the second queue.

19 . The memory system of claim 18 , wherein the memory controller is configured to:
when the first queue is in an empty state, shut off power to a command pin configured to transmit the control information among the plurality of pins, and
when the second queue is in an empty state, shut off power to a data pin configured to transmit and receive the data among the plurality of pins.

20 . The memory system of claim 19 ,
wherein the plurality of pins further includes a read enable pin and a reference voltage pin which are connected to the memory apparatus, and
wherein the memory controller is configured to:
when the second queue is in the empty state, shut off power to the data pin and the read enable pin together, and
when the first queue and the second queue are in the empty state, shut off power to the reference voltage pin.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Lee Junyeol
• Kim Hyungjin
• Lee Chulseung

Classifications

• G06F3/0679

  Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP] · CPC title

• G06F3/0659 Primary

  Command handling arrangements, e.g. command buffers, queues, command scheduling · CPC title

• G06F3/0625 Primary

  Power saving in storage systems · CPC title

• G06F2212/1024

  Latency reduction · CPC title

• G06F2212/1028

  Power efficiency · CPC title