Integrated circuit on chip regulator output power-ground shorts detector

Patent metadata

Field	Value
Publication number	US-2025383677-A1
Application number	US-202418744193-A
Country	US
Kind code	A1
Filing date	Jun 14, 2024
Priority date	Jun 14, 2024
Publication date	Dec 18, 2025
Grant date	—

Abstract

Embodiments of the present disclosure provide enhanced systems and methods for detecting output power-ground shorts in on-chip voltage regulators, such as used for phase-locked loop (PLL) circuits in integrated circuit (IC) chips. A disclosed regulator output power-ground short detector can detect both initial output power-ground shorts of the on-chip voltage regulator including initial high resistance output power-ground shorts, and output power-ground shorts that can occur in a user's environment and degrade over time for example, resulting from a degrading or failing output voltage regulator analog (VRA) capacitor. In an embodiment, the regulator output power-ground short detector detects predefined threshold voltage offsets of a degraded power-ground short over time, and transmits warning notifications that enable corrective actions, such as repair or replacement before failure of the PLL circuits.

First claim

What is claimed is:

1 . A method comprising:
comparing, by a comparator, an output voltage of an on-chip voltage regulator with a predefined voltage reference to detect a threshold voltage offset, wherein the threshold voltage offset represents an output power-ground short; and transmitting, by an error and control logic, a warning notification based on the threshold voltage offset.

2 . The method of claim 1 , further comprising:
comparing, by a series of comparators that includes the comparator, the output voltage with a plurality of predefined voltage references; and detecting respective threshold voltage offsets by the series of comparators to monitor degraded values of the output power-ground short.

3 . The method of claim 2 , further comprising transmitting, by the error and control logic, warning notifications based on the degraded values of the output power-ground short.

4 . The method of claim 2 , further comprising producing, by a voltage divider, the plurality of predefined voltage references, wherein the voltage divider comprises a plurality of series-connected resistors coupled between a voltage reference input to the on-chip voltage regulator and a ground potential, and the plurality of predefined voltage references are produced at respective taps between the series-connected resistors.

5 . The method of claim 1 , further comprising for an initial chip test mode, limiting, by a current limiting circuitry of the on-chip voltage regulator, an output current of the on-chip voltage regulator; and comparing, by the comparator, the output voltage and the predefined reference voltage, to detect the output power-ground short.

6 . The method of claim 5 , wherein the on-chip voltage regulator comprises a plurality of output current tiles supplying the output current, further comprising the current limiting circuitry selectively enabling at least one of the plurality of output current tiles, and disabling other ones of the plurality of output current tiles, to limit the output current of the on-chip voltage regulator for the initial chip test mode.

7 . The method of claim 6 , wherein the current limiting circuitry comprises a plurality of enable transistors, with a respective enable transistor connected in series with an associated output current tile, and the enable transistors receiving a gate control signal to turn on the enable transistors for selectively enabling at least one of the plurality of output current tiles.

8 . The method of claim 5 , wherein the on-chip voltage regulator comprises a plurality of output current tiles supplying the output current, and the current limiting circuitry selectively provides a reference current to the plurality of output current tiles to limit the output current of the on-chip voltage regulator for the initial chip test mode.

9 . The method of claim 8 , wherein the current limiting circuitry comprises a current source coupled to a catch diode, a reference transistor coupled to the catch diode to provide the reference current to the plurality of output current tiles based on the current source, and a current limiting transistor selectively coupled to the catch diode by a throttle select switch to limit the reference current provided to the plurality of output current tiles for the initial chip test mode.

10 . The method of claim 5 , further comprising applying, by the error and control logic, a control input to phase-locked-loop (PLL) circuits receiving the output voltage of the on-chip voltage regulator to provide a reset mode for the PLL circuits to limit a current load of the PLL circuits for the initial chip test mode.

11 . A system, comprising:
an on-chip voltage regulator configured to receive a reference voltage and provide an output voltage; a comparator configured to compare the output voltage of the on-chip voltage regulator with a predefined reference voltage to detect a threshold voltage offset, wherein the threshold voltage offset represents an output power-ground short; and an error and control logic configured to transmit a warning notification based on the threshold voltage offset.

12 . The system of claim 11 , further comprising:
a series of comparators configured to compare the output voltage with a plurality of predefined voltage references, and detect respective threshold voltage offsets by the series of comparators, to monitor degraded values of the output power-ground short; and wherein the error and control logic is configured to transmit a series of warning notifications, based on the degraded values of the output power-ground short.

13 . The system of claim 12 , further comprising:
a voltage divider configured to produce the plurality of predefined voltage references, wherein the voltage divider comprises a plurality of series-connected resistors coupled between a voltage reference input to the on-chip voltage regulator and a ground potential; and wherein the plurality of predefined voltage references are produced at taps between the series-connected resistors.

14 . The system of claim 13 , further comprising a multiplexer coupled to the voltage divider, wherein the multiplexer is configured to receive the plurality of predefined voltage references and select a predefined voltage reference to compare to the output voltage for an initial chip test mode.

15 . The system of claim 11 , wherein the on-chip voltage regulator comprises a plurality of output current tiles supplying an output current of the on-chip voltage regulator, and a current limiting circuitry configured to limit the output current of the on-chip voltage regulator for an initial chip test mode.

16 . The system of claim 15 , wherein the current limiting circuitry comprises a plurality of enable transistors, wherein the enable transistors are connected in series with associated output current tiles, and the enable transistors are configured to receive a control gate input to selectively enable an associated output current tile to supply output current for the initial chip test mode.

17 . The system of claim 15 , wherein the current limiting circuitry is configured to apply a reference current to the plurality of output current tiles to limit the output current supplied by the plurality of output current tiles for the initial chip test mode.

18 . The system of claim 17 , wherein the current limiting circuitry comprises a current source coupled to a catch diode, a reference transistor coupled to the catch diode to provide the reference current to the plurality of output current tiles based on the current source; and a current limiting transistor selectively coupled to the catch diode by a throttle select switch, to limit the reference current provided by the reference transistor for the initial chip test mode.

19 . The system of claim 18 , wherein the catch diode, the reference transistor, and the current limiting transistor comprise metal-oxide semiconductor (MOS) p-type field effect transistors (PFETs), the catch diode is a catch diode PFET, and the reference transistor is a reference PFET, and wherein a reference voltage is coupled to a source of the PFETs, and a gate and a drain of the catch diode PFET are coupled together to the current source and coupled to a gate of the reference PFET.

20 . An integrated circuit, comprising:
an on-chip voltage regulator configured to receive a reference voltage and provide an output voltage; a comparator configured to compare the output voltage of the on-chip voltage regulator with a predefined reference volta

Assignees

• IBM

Inventors

• Strom James
• Kesselring Grant P
• Borkenhagen John
• Chica Joshua M

Classifications

• G05F1/59

  including plural semiconductor devices as final control devices for a single load · CPC title

• G05F1/565 Primary

  sensing a condition of the system or its load in addition to means responsive to deviations in the output of the system, e.g. current, voltage, power factor (G05F1/563 takes precedence) · CPC title

• H03K17/0822

  in field-effect transistor switches · CPC title

• G05F3/262

  using field-effect transistors only · CPC title

• H03K17/223 Primary

  in field-effect transistor switches · CPC title