Semiconductor memory device

Patent metadata

Field	Value
Publication number	US-2025380402-A1
Application number	US-202519019816-A
Country	US
Kind code	A1
Filing date	Jan 14, 2025
Priority date	Jun 7, 2024
Publication date	Dec 11, 2025
Grant date	—

Abstract

A semiconductor memory device includes a data storage pattern on a substrate, a buried contact on the data storage pattern, a bit-line spaced apart from the buried contact in a first direction perpendicular to an upper surface of the substrate and extending in a second direction parallel to the upper surface of the substrate, a channel pattern between the buried contact and the bit-line and connected to the buried contact and the bit-line, and a word-line on the channel pattern and extending in a third direction parallel to the upper surface of the substrate and intersecting the second direction. The channel pattern includes a first surface contacting the buried contact and a second surface contacting the bit-line. A width in the second direction of the first surface of the channel pattern is greater than a width in the second direction of the second surface of the channel pattern.

First claim

What is claimed is:

1 . A semiconductor memory device, comprising:
a data storage pattern on a substrate; a buried contact on the data storage pattern; a bit-line spaced apart from the buried contact in a first direction and extending in a second direction; a channel pattern between the buried contact and the bit-line and electrically connected to the buried contact and the bit-line; and a word-line on the channel pattern and extending in a third direction, wherein the channel pattern includes a first surface contacting the buried contact and a second surface contacting the bit-line, wherein a width in the second direction of the first surface of the channel pattern is greater than a width in the second direction of the second surface of the channel pattern.

2 . The semiconductor memory device of claim 1 , further comprising a gate insulating pattern between the channel pattern and the word-line and extending along a profile of the channel pattern.

3 . The semiconductor memory device of claim 2 , wherein a distance in the first direction from the buried contact to the second surface of the channel pattern is smaller than a distance in the first direction from the buried contact to an upper surface of the gate insulating pattern.

4 . The semiconductor memory device of claim 2 , wherein the gate insulating pattern does not directly contact the buried contact.

5 . The semiconductor memory device of claim 1 , wherein a length in the second direction of the buried contact is different from the length in the second direction of the first surface of the channel pattern.

6 . The semiconductor memory device of claim 1 , wherein the first surface of the channel pattern is only on the buried contact.

7 . The semiconductor memory device of claim 1 , wherein at least a portion of the first surface of the channel pattern does not contact the buried contact.

8 . The semiconductor memory device of claim 1 , wherein the channel pattern includes a first channel pattern and a second channel pattern spaced apart from each other in the second direction,
wherein a mold insulating film is between the first channel pattern and the second channel pattern, and wherein the first channel pattern and the second channel pattern have a symmetrical structure with respect to each other around the mold insulating film.

9 . The semiconductor memory device of claim 8 , wherein the mold insulating film includes a first mold insulating film and a second mold insulating film sequentially stacked in the first direction,
wherein at least a portion of the first mold insulating film is in direct contact with the buried contact, and wherein the second mold insulating film comprises nitrogen.

10 . The semiconductor memory device of claim 1 , wherein the channel pattern includes a first portion extending in the first direction and a second portion extending in the second direction,
wherein a thickness in the second direction of the first portion of the channel pattern is equal to a thickness in the first direction of the second portion of the channel pattern.

11 . The semiconductor memory device of claim 10 , wherein the first portion of the channel pattern does not directly contact the buried contact, and
wherein the second portion of the channel pattern is in direct contact with the buried contact and extends along a profile of the buried contact.

12 . The semiconductor memory device of claim 1 , further comprising a peripheral circuit element on a lower surface of the data storage pattern and electrically connected to the data storage pattern.

13 . A semiconductor memory device, comprising:
a data storage pattern on a substrate; a buried contact on the data storage pattern; a channel pattern on an upper surface of the buried contact and electrically connected to the buried contact; a bit-line on the channel pattern, electrically connected to the channel pattern, and extending in a first direction parallel to an upper surface of the substrate; and a word-line on the channel pattern and between the buried contact and the bit-line, wherein the word-line extends in a second direction parallel to the upper surface of the substrate and intersecting the first direction, wherein the channel pattern includes a horizontal portion and a vertical portion connected to the horizontal portion, wherein the horizontal portion of the channel pattern extends in the first direction and along an upper surface of the buried contact, and wherein the vertical portion of the channel pattern extends from the horizontal portion of the channel pattern in a third direction perpendicular to the upper surface of the substrate.

14 . The semiconductor memory device of claim 13 , wherein at least a portion of the horizontal portion of the channel pattern does not contact the buried contact.

15 . The semiconductor memory device of claim 13 , further comprising a gate insulating pattern between the channel pattern and the word-line, and
wherein the gate insulating pattern does not directly contact the buried contact.

16 . The semiconductor memory device of claim 13 , wherein a thickness in the third direction of the horizontal portion of the channel pattern is equal to a thickness in the first direction of the vertical portion of the channel pattern.

17 . A semiconductor memory device, comprising:
a peripheral circuit element on a substrate; a data storage pattern on the peripheral circuit element; a buried contact on the data storage pattern; a bit-line spaced apart from the buried contact in a first direction and extending in a second direction; a channel pattern between the buried contact and the bit-line and contacting the buried contact and the bit-line; and a word-line on the channel pattern and extending in a third direction, wherein the channel pattern includes a first surface contacting the buried contact and a second surface contacting the bit-line, and wherein a width in the second direction of the first surface of the channel pattern is greater than a width in the second direction of the second surface of the channel pattern.

18 . The semiconductor memory device of claim 17 , wherein the data storage pattern is between the channel pattern and the peripheral circuit element.

19 . The semiconductor memory device of claim 17 , wherein the data storage pattern is between the buried contact and the peripheral circuit element.

20 . The semiconductor memory device of claim 17 , wherein the data storage pattern is between the bit-line and the peripheral circuit element.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Park Sung Joon
• Terai Masayuki

Classifications

• H10B43/27

  the channels comprising vertical portions, e.g. U-shaped channels · CPC title

• H10B12/50

  Peripheral circuit region structures · CPC title

• H10B12/05

  Making the transistor · CPC title

• H10B12/33 Primary

  the capacitor extending under the transistor · CPC title

• H10D30/6757

  characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715) · CPC title