Asynchronous multi-level signal sampling

Patent metadata

Field	Value
Publication number	US-2025378862-A1
Application number	US-202519221198-A
Country	US
Kind code	A1
Filing date	May 28, 2025
Priority date	Jun 6, 2024
Publication date	Dec 11, 2025
Grant date	—

Abstract

Methods, systems, and devices for asynchronous multi-level signal sampling are described. A system may generate a first clock signal by delaying the master clock signal by a first duration that is based on a first propagation delay associated with a first amplifier for a data signal. The system may generate a second clock signal by delaying the master clock signal by a second duration that is based on a second propagation delay associated with a second amplifier for the data signal. The system may sample, by a first sampling circuit based on the first clock signal, a first amplified data signal outputted by the first amplifier. And the system may sample, by a second sampling circuit based on the second clock signal, a second amplified data signal outputted by the second amplifier.

First claim

What is claimed is:

1 . A method, comprising:
generating a master clock signal for a memory system; generating a first clock signal by delaying the master clock signal by a first duration that is based at least in part on a first propagation delay associated with a first amplifier configured to amplify a voltage difference between a received data signal and a first reference voltage; generating a second clock signal by delaying the master clock signal by a second duration that is based at least in part on a second propagation delay associated with a second amplifier configured to amplify a voltage difference between the received data signal and a second reference voltage; sampling, by a first sampling circuit based at least in part on the first clock signal, a first amplified data signal outputted by the first amplifier; and sampling, by a second sampling circuit based at least in part on the second clock signal, a second amplified data signal outputted by the second amplifier.

2 . The method of claim 1 , further comprising:
determining a symbol value for the data signal based at least in part on a first sampled value of the first amplified data signal and on a second sampled value of the second amplified data signal.

3 . The method of claim 1 , further comprising:
inputting the master clock signal into first delay circuit configured to delay the master clock signal by the first duration, wherein the first clock signal is generated by the first delay circuit; and inputting the master clock signal into a second delay circuit configured to delay the master clock signal by the second duration, wherein the second clock signal is generated by the second delay circuit.

4 . The method of claim 3 , further comprising:
inputting the first clock signal into the first sampling circuit, wherein the first amplified data signal is sampled based at least in part on inputting the first clock signal into the first sampling circuit; and inputting the second clock signal into the second sampling circuit, wherein the second amplified data signal is sampled based at least in part on inputting the second clock signal into the second sampling circuit.

5 . The method of claim 1 , further comprising:
generating a third clock signal by delaying the master clock signal by a third duration that is based at least in part on a third propagation delay associated with a third amplifier configured to amplify a voltage difference between the received data signal and a third reference voltage; and sampling, by a third sampling circuit based at least in part on the third clock signal, a third amplified data signal outputted by the third amplifier.

6 . The method of claim 1 , wherein the data signal comprises a pulse amplitude modulated (PAM) signal comprising a highest voltage level, a middle voltage level, and a lowest voltage level.

7 . The method of claim 6 , wherein the first reference voltage is between the highest voltage level of the data signal and the middle voltage level of the data signal, and wherein the second reference voltage is between the middle voltage level of the data signal and the lowest voltage level of the data signal.

8 . The method of claim 1 , wherein the first clock signal and the second clock signal have a same frequency and a same duty cycle.

9 . An apparatus, comprising:
a clock circuit configured to generate a master clock signal; a first delay circuit configured to output a first clock signal by being configured to delay the master clock signal by a first duration that is based at least in part on a first propagation delay associated with a first amplifier configured to receive a data signal; a second delay circuit configured to output a second clock signal by being configured to delay the master clock signal by a second duration that is based at least in part on a second propagation delay associated with a second amplifier configured to receive the data signal; a first sampling circuit configured to sample, based at least in part on the first clock signal, a first amplified data signal outputted by the first amplifier; and a second sampling circuit configured to sample, based at least in part on the second clock signal, a second amplified data signal outputted by the second amplifier.

10 . The apparatus, of claim 9 , further comprising:
a decoder configured to determine a symbol value for the data signal based at least in part on a first sampled value of the first amplified data signal and on a second sampled value of the second amplified data signal.

11 . The apparatus, of claim 9 , wherein the first delay circuit comprises one or more inverters, and wherein the second delay circuit comprises one or more inverters.

12 . The apparatus of claim 9 , wherein the first sampling circuit is coupled with the first amplifier and the first delay circuit, and wherein the second sampling circuit is coupled with the second amplifier and the second delay circuit.

13 . The apparatus of claim 9 , wherein a first input terminal of the first amplifier is coupled with a second input terminal of the second amplifier, and wherein the first input terminal and the second input terminal are configured to receive the data signal.

14 . The apparatus, of claim 9 , wherein the first amplifier is configured to amplify a voltage difference between the data signal and a first reference voltage, and wherein the second amplifier is configured to amplify a voltage difference between the data signal and a second reference voltage.

15 . The apparatus of claim 14 , wherein the data signal comprises a pulse amplitude modulated (PAM) signal comprising a highest voltage level, a middle voltage level, and a lowest voltage level, wherein the first reference voltage is between the highest voltage level of the data signal and the middle voltage level of the data signal, and wherein the second reference voltage is between the middle voltage level of the data signal and the lowest voltage level of the data signal.

16 . The apparatus of claim 9 , further comprising:
a third delay circuit configured to output a third clock signal by being configured to delay the master clock signal by a third duration that is based at least in part on a third propagation delay associated with a third amplifier configured to receive the data signal; and a third sampling circuit configured to sample, based at least in part on the third clock signal, a third amplified data signal outputted by the third amplifier.

17 . A non-transitory computer-readable medium storing code comprising instructions which, when executed by one or more processors of an apparatus, cause the apparatus to:
generate a master clock signal for a memory system; generate a first clock signal by delaying the master clock signal by a first duration that is based at least in part on a first propagation delay associated with a first amplifier configured to amplify a voltage difference between a received data signal and a first reference voltage; generate a second clock signal by delaying the master clock signal by a second duration that is based at least in part on a second propagation delay associated with a second amplifier configured to amplify a voltage difference between the received data signal and a second reference voltage; sample, by a first sampling circuit based at least in part on the first clock signal, a first amplified data signal outputted by the first amplifier; and sample, by a second sampling circuit based at least in part on the second clock signal, a second amplified data signal outputted by the se

Assignees

• Micron Technology Inc

Inventors

• Brox Martin
• Bach Martin
• Nenadovic Miljana
• Madhewar Hemant
• Balakrishnan Mani
• Hein Thomas

Classifications

• G11C7/1066

  Output synchronization · CPC title

• G11C7/1084

  Data input buffers, e.g. comprising level conversion circuits, circuits for adapting load · CPC title

• G11C7/1093

  Input synchronization · CPC title

• H03K5/133

  using a chain of active delay devices · CPC title

• G06F1/08

  Clock generators with changeable or programmable clock frequency · CPC title