Apparatus and computer-implemented method for determining a memory plan for executing operations

Patent metadata

Field	Value
Publication number	US-2025378317-A1
Application number	US-202519209298-A
Country	US
Kind code	A1
Filing date	May 15, 2025
Priority date	May 24, 2024
Publication date	Dec 11, 2025
Grant date	—

Abstract

An apparatus and computer-implemented method for determining a memory plan for executing operations, in particular of an artificial neural network. A list of memory areas required for executing the operations is created, wherein, depending on the list, it is determined for the operations which memory areas must be present in a first memory for executing the particular operation and which memory areas may be present in a second memory during the execution of the particular operation, wherein the memory plan is determined depending on whether a memory area must be present in the main memory for execution or may be present in the secondary memory.

First claim

1 - 5 . (canceled)

6 . A computer-implemented method for determining a memory plan for executing operations of an artificial neural network, the method comprising the following steps:
creating a list of memory areas required for executing the operations; depending on the list, determining for the operations which memory areas must be present in a first memory for executing a respective operation and which memory areas may be present in a second memory during the execution of the respective operation; determining the memory plan depending on whether a memory area must be present in the first memory for execution or may be present in the second memory; for each operation, determining an assignment of the memory areas one of the the first memory and to the second memory; for each operation, marking the memory areas in the list that do not have to be in the first memory are marked; and determining the memory plan depending on the list with the marked memory areas, and determining the assignment that minimizes a number of transfers of memory areas between the first memory and the second memory.

7 . The method according to claim 6 , wherein the assignment is determined using a satisfiability modulo theories solver.

8 . The method according to claim 6 , wherein the memory areas for executing the operations are provided according to the memory plan, wherein certain of the memory areas are transferred from the first memory to the second memory or are transferred from the second memory to the first memory according to the memory plan.

9 . An apparatus for determining a memory plan for executing operations of an artificial neural network, the apparatus comprising:
at least one processor; and at least one memory, wherein the at least one memory includes instructions which can be executed by the at least one processor, and, upon execution of which by the at least one processor, the following steps are executed:
creating a list of memory areas required for executing the operations,
depending on the list, determining for the operations which memory areas must be present in a first memory for executing a respective operation and which memory areas may be present in a second memory during the execution of the respective operation,
determining the memory plan depending on whether a memory area must be present in the first memory for execution or may be present in the second memory,
for each operation, determining an assignment of the memory areas one of the the first memory and to the second memory,
for each operation, marking the memory areas in the list that do not have to be in the first memory are marked, and
determining the memory plan depending on the list with the marked memory areas, and determining the assignment that minimizes a number of transfers of memory areas between the first memory and the second memory.

10 . A non-transitory storage medium on which is stored a computer program including computer-readable instructions for determining a memory plan for executing operations of an artificial neural network, the instructions, when executed by at least one processor, causing the at least one comprising the following steps:
creating a list of memory areas required for executing the operations; depending on the list, determining for the operations which memory areas must be present in a first memory for executing a respective operation and which memory areas may be present in a second memory during the execution of the respective operation; determining the memory plan depending on whether a memory area must be present in the first memory for execution or may be present in the second memory; for each operation, determining an assignment of the memory areas one of the the first memory and to the second memory; for each operation, marking the memory areas in the list that do not have to be in the first memory are marked; and determining the memory plan depending on the list with the marked memory areas, and determining the assignment that minimizes a number of transfers of memory areas between the first memory and the second memory.

Assignees

• Bosch Gmbh Robert

Inventors

• Wagner Benjamin
• Vo Duy Khoi
• Boblest Sebastian
• Markwart Sven
• Hjort Ulrik

Classifications

• G06N3/063 Primary

  using electronic means · CPC title

• G06F3/0614

  Improving the reliability of storage systems · CPC title

• G06F3/0604 Primary

  Improving or facilitating administration, e.g. storage management · CPC title