Display substrate and manufacturing method therefor, and display device

US2025374773A1 · US · A1

Patent metadata
FieldValue
Publication numberUS-2025374773-A1
Application numberUS-202519300695-A
CountryUS
Kind codeA1
Filing dateAug 15, 2025
Priority dateJun 19, 2020
Publication dateDec 4, 2025
Grant date

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  1. Title

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  5. First independent claim

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  6. CPC / IPC classifications

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Abstract

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A display substrate includes: a driving backplane, a first electrode layer, an electric leakage cutoff layer, a light-emitting functional layer and a second electrode layer. The first electrode layer includes a plurality of first electrodes distributed in an array, there is a spacing groove between two adjacent first electrodes, a first electrode of the plurality of first electrodes includes a flat middle portion, a thickness of the light-emitting functional layer located between a gentle portion of the second electrode layer and the middle portion is d0 in a direction perpendicular to the driving backplane, the minimum value of the sum of a thickness of the electric leakage cutoff layer lapping over the middle portion and a thickness of the middle portion is d1, and a ratio of d1 to d0 is 0.3 to 1.

First claim

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1 . A display substrate, comprising: a driving backplane comprising a driving structure layer and a planarization layer overlaying the driving structure layer, wherein a via hole is provided in the planarization layer, and the planarization layer has a flat surface outside the via hole; a first electrode layer located at one side of the planarization layer away from the driving structure layer, wherein the first electrode layer comprises a plurality of first electrodes distributed in an array, there is a spacing groove between two adjacent first electrodes, a first electrode of the plurality of first electrodes comprises a flat middle portion, and the first electrode is electrically connected to the driving structure layer through the via hole; an electric leakage cutoff layer located at one side of the first electrode layer away from the driving backplane, wherein the electric leakage cutoff layer is located between two adjacent first electrodes, and the electric leakage cutoff layer laps over a surface of at least one side of the middle portion away from the driving backplane; a light-emitting functional layer located at one side of the electric leakage cutoff layer and the first electrode layer away from the driving backplane; and a second electrode layer located at one side of the light-emitting functional layer away from the driving backplane; wherein the second electrode layer comprises a gentle portion corresponding to the middle portion, a thickness of the light-emitting functional layer located between the gentle portion and the middle portion is d0 in a direction perpendicular to the driving backplane, a minimum value of a sum of a thickness of the electric leakage cutoff layer lapping over the middle portion and a thickness of the middle portion is d1, and a ratio of d1 to d0 is 0.3 to 1. 2 . The display substrate according to claim 1 , wherein the planarization layer is an inorganic layer. 3 . The display substrate according to claim 1 , wherein the electric leakage cutoff layer is provided with a cutoff groove corresponding to the spacing groove. 4 . The display substrate according to claim 3 , wherein a depth of the cutoff groove is greater than or equal to the thickness of the middle portion. 5 . The display substrate according to claim 3 , wherein a width of the cutoff groove is 0.3 μm to 1.5 μm. 6 . The display substrate according to claim 1 , wherein the thickness of the electric leakage cutoff layer lapping over the at least one side of the middle portion is less than the thickness of the middle portion. 7 . The display substrate according to claim 1 , wherein the second electrode layer comprises a plurality of gentle portions corresponding to middle portions of the plurality of first electrodes and connecting portions located between adjacent gentle portions, and a connecting portion of the connecting portions comprises a concave portion and convex portions located at two sides of the concave portion. 8 . The display substrate according to claim 7 , wherein a lowest point of the concave portion is closer to a side of the driving backplane than the plurality of gentle portions. 9 . The display substrate according to claim 7 , wherein a lowest point of the concave portion is above the electric leakage cutoff layer. 10 . The display substrate according to claim 7 , wherein a slope angle of a side wall of the concave portion is smaller than or equal to 65°. 11 . The display substrate according to claim 7 , wherein a depth of the concave portion is greater than protrusion heights of the convex portions. 12 . The display substrate according to claim 7 , wherein top surfaces of the convex portions are flat surfaces. 13 . The display substrate according to claim 7 , wherein the convex portions are located on one side of the plurality of gentle portions away from the driving backplane. 14 . The display substrate according to claim 7 , wherein the first electrode further comprises a climbing portion surrounding the middle portion, and an orthographic projection of the climbing portion on the driving backplane is within an orthographic projection of a corresponding convex portion of the convex portions on the driving backplane. 15 . The display substrate according to claim 7 , wherein an orthographic projection of the electric leakage cutoff layer lapping over the at least one side of the middle portion is within an orthographic projection of the convex portions on the driving backplane. 16 . The display substrate according to claim 7 , wherein the electric leakage cutoff layer is provided with a cutoff groove corresponding to the spacing groove, and a depth of the cutoff groove is greater than a thickness of the concave portion. 17 . The display substrate according to claim 1 , wherein the ratio of d1 to d0 is 0.3 to 0.4. 18 . The display substrate according to claim 1 , wherein the ratio of d1 to d0 is 0.4 to 0.5. 19 . The display substrate according to claim 1 , wherein the ratio of d1 to d0 is 0.5 to 0.6. 20 . The display substrate according to claim 1 , wherein the ratio of d1 to d0 is 0.6 to 0.7. 21 . The display substrate according to claim 1 , wherein the ratio of d1 to d0 is 0.7 to 0.8. 22 . The display substrate according to claim 1 , wherein the ratio of d1 to d0 is 0.8 to 0.9. 23 . The display substrate according to claim 1 , wherein the ratio of d1 to d0 is 0.9 to 1. 24 . The display substrate according to claim 1 , wherein the thickness of the electric leakage cutoff layer lapping over the surface of the middle portion is 300 angstroms to 800 angstroms. 25 . The display substrate according to claim 1 , wherein a width of a lap-over area between the electric leakage cutoff layer and the middle portion is 0.05 μm to 0.3 μm. 26 . The display substrate according to claim 1 , wherein the light-emitting functional layer comprises a hole injection layer, a hole transport layer, a first light-emitting layer, a second light-emitting layer, an intermediate layer, a third light-emitting layer, a hole blocking layer, an electron transport layer and an electron injection layer stacked from the first electrode towards one side of the second electrode layer.

Assignees

Inventors

Classifications

  • Manufacture or treatment · CPC title

  • Pixel-defining structures or layers, e.g. banks · CPC title

  • comprising red-green-blue [RGB] subpixels · CPC title

  • H10K71/00Primary

    Manufacture or treatment specially adapted for the organic devices covered by this subclass · CPC title

  • characterised by the geometrical arrangement of the RGB subpixels · CPC title

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What does patent US2025374773A1 cover?
A display substrate includes: a driving backplane, a first electrode layer, an electric leakage cutoff layer, a light-emitting functional layer and a second electrode layer. The first electrode layer includes a plurality of first electrodes distributed in an array, there is a spacing groove between two adjacent first electrodes, a first electrode of the plurality of first electrodes includes a …
Who is the assignee on this patent?
Boe Technology Group Co Ltd
What technology area does this patent fall under?
Primary CPC classification H10K71/00. Mapped technology areas include Electricity.
When was this patent published?
Publication date Thu Dec 04 2025 00:00:00 GMT+0000 (Coordinated Universal Time) (A1). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).