Method for compensating for clock frequency deviation between two ends of link, and communication port

Patent metadata

Field	Value
Publication number	US-2025365125-A1
Application number	US-202519287062-A
Country	US
Kind code	A1
Filing date	Jul 31, 2025
Priority date	Feb 3, 2023
Publication date	Nov 27, 2025
Grant date	—

Abstract

This application discloses a method for compensating for a clock frequency deviation between two ends of a link, and a communication port. The method may be applied to a first port. The first port detects a quantity of protocol-aware signal extenders in a link between the first port and a second port, and generates a padding packet based on the quantity of protocol-aware signal extenders in the link. Then, the first port inserts the padding packet into a data stream to be sent to the second port.

First claim

What is claimed is:

1 . A method for compensating for a clock frequency deviation between two ends of a link, comprising:
detecting, by a first port, a quantity of protocol-aware signal extenders in a link between the first port and a second port; generating, by the first port, a padding packet based on the quantity of signal extenders in the link, wherein the padding packet is used for compensating for a clock frequency deviation between the first port and the second port; and inserting, by the first port, the padding packet into a data stream to be sent to the second port.

2 . The method according to claim 1 , wherein the padding packet comprises at least one padding unit, and generating, by the first port, the padding packet based on the quantity of signal extenders in the link comprises:
determining, by the first port, a quantity of padding units in the padding packet based on the quantity of signal extenders in the link; and generating, by the first port, the padding packet based on the quantity of padding units.

3 . The method according to claim 2 , wherein the quantity of padding units in the padding packet is greater than the quantity of signal extenders in the link.

4 . The method according to claim 3 , wherein a larger quantity of signal extenders in the link indicates a larger quantity of padding units in the padding packet.

5 . The method according to claim 4 , wherein
when the link comprises no signal extender, the quantity of padding units in the padding packet is x; and each time one signal extender is added to the link, the quantity of padding units in the padding packet is increased by y, wherein both x and y are positive integers.

6 . The method according to claim 1 , wherein the first port is a port on a first chip, and the second port is a port on a second chip.

7 . The method according to claim 1 , wherein the padding packet comprises one or both of an end field or a control field.

8 . The method according to claim 1 , wherein the first port and the second port use a same clock source, or the first port and the second port use different clock sources.

9 . A first apparatus, comprising:
a memory configured to store instructions; and at least one processor coupled to the memory and configured to execute the instructions to cause the apparatus to: detect a quantity of protocol-aware signal extenders in a link between the first apparatus and a second apparatus; generate a padding packet based on the quantity of signal extenders in the link, wherein the padding packet is used for compensating for a clock frequency deviation between the first apparatus and the second apparatus; and insert the padding packet into a data stream to be sent to the second apparatus.

10 . The apparatus according to claim 8 , wherein the at least one processor coupled to the memory and configured to execute the further instructions to cause the apparatus to:
determine a quantity of padding units in the padding packet based on the quantity of signal extenders in the link; and generate the padding packet based on the quantity of padding units.

11 . The apparatus according to claim 10 , wherein the quantity of padding units in the padding packet is greater than the quantity of signal extenders in the link.

12 . The apparatus according to claim 11 , wherein a larger quantity of signal extenders in the link indicates a larger quantity of padding units in the padding packet.

13 . The apparatus according to claim 12 , wherein
when the link comprises no signal extender, the quantity of padding units in the padding packet is x; and each time one signal extender is added to the link, the quantity of padding units in the padding packet is increased by y, wherein both x and y are positive integers.

14 . The apparatus according to claim 9 , wherein the first port is a port on a first chip, and the second port is a port on a second chip.

15 . The apparatus according to claim 9 , wherein the padding packet comprises one or both of an end field or a control field.

16 . The apparatus according to claim 9 , wherein the first port and the second port use a same clock source, or the first port and the second port use different clock sources.

17 . A computer program product comprising instructions that are stored on a non-transitory computer-readable storage medium and that, when executed by at least one processor, cause an apparatus to:
detect a quantity of protocol-aware signal extenders in a link between the first apparatus and a second apparatus; generate a padding packet based on the quantity of signal extenders in the link, wherein the padding packet is used for compensating for a clock frequency deviation between a first apparatus and the second apparatus; and insert the padding packet into a data stream to be sent to the second apparatus.

18 . The computer program product according to claim 17 , wherein when executed by at least one processor, further cause an apparatus to:
determine a quantity of padding units in the padding packet based on the quantity of signal extenders in the link; and generate the padding packet based on the quantity of padding units.

19 . The computer program product according to claim 18 , wherein the quantity of padding units in the padding packet is greater than the quantity of signal extenders in the link.

20 . The computer program product according to claim 19 , wherein a larger quantity of signal extenders in the link indicates a larger quantity of padding units in the padding packet.

Assignees

• Huawei Tech Co Ltd

Inventors

• Luo Junping
• Pan Wei
• Nie Er

Classifications

• H04L1/002

  Algorithms with memory of the previous states, e.g. Markovian models · CPC title

• H04L1/0008 Primary

  by supplementing frame payload, e.g. with padding bits · CPC title

• H04L1/00

  Arrangements for detecting or preventing errors in the information received {(correcting synchronisation H04L7/00)} · CPC title

• H04L7/0012

  by comparing receiver clock with transmitter clock · CPC title

• H04L7/0008 Primary

  Synchronisation information channels, e.g. clock distribution lines · CPC title