Semiconductor devices with reduced effect of capacitive coupling

Patent metadata

Field	Value
Publication number	US-2025364399-A1
Application number	US-202519287416-A
Country	US
Kind code	A1
Filing date	Jul 31, 2025
Priority date	May 26, 2022
Publication date	Nov 27, 2025
Grant date	—

Abstract

A semiconductor device includes a first source/drain structure and a second source/drain structure of a first transistor. The semiconductor device includes a first source/drain structure and a second source/drain structure of a first transistor. The semiconductor device includes a third source/drain structure and a fourth source/drain structure of a second transistor. The second source/drain structure and the third source/drain structure merges as a common source/drain structure. The semiconductor device includes a first interconnect structure extending along a first lateral direction and disposed above the common source/drain structure. The semiconductor device includes a first dielectric structure interposed between the first interconnect structure and the common source/drain structure.

First claim

What is claimed is:

1 . A method, comprising:
forming an active region over a substrate, wherein the active region extends along a first lateral direction; forming a first gate structure and a second gate structure, wherein the first gate structure and second gate structure each extend along a second lateral direction perpendicular to the first lateral direction; forming a dielectric structure overlaying a first portion of the active region that is interposed between the first and second gate structures; and forming a first interconnect structure, a second interconnect structure, and a third interconnect structure over the first portion, a second portion, and a third portion of the active region, respectively, with the dielectric structure interposed between the first portion of the active region and the first interconnect structure, wherein the first to third interconnect structures all extend along the second lateral direction.

2 . The method of claim 1 , wherein the dielectric structure is configured to electrically isolate the first portion of the active region from the first interconnect structure.

3 . The method of claim 1 , further comprising:
forming a via structure connected to the first interconnect structure; and forming a fourth interconnect structure connected to the via structure.

4 . The method of claim 3 , wherein the fourth interconnect structure extends along the first lateral direction and is configured at a power supply voltage or a fixed voltage.

5 . The method of claim 1 , further comprising:
forming a plurality of via structures over each of the second interconnect structure and the third interconnect structure; and forming a plurality of interconnect structures over each of the second interconnect structure and the third interconnect structure.

6 . The method of claim 1 , wherein the dielectric extends in the first and second lateral directions beyond edges of the first portion of the active region

7 . The method of claim 1 , wherein the dielectric extends in at least the first lateral direction beyond edges of the first interconnect structure.

8 . The method of claim 1 , wherein the first interconnect structure is configured at a floating voltage.

9 . The method of claim 1 , wherein the dielectric structure is a first dielectric structure, the method further comprises at least one of:
forming a second dielectric structure overlaying the second portion of the active region, wherein the second dielectric structure is interposed between the second portion of the active region and the second interconnect structure; or forming a third dielectric structure overlaying the third portion of the active region, wherein the third dielectric structure is interposed between the third portion of the active region and the third interconnect structure.

10 . The method of claim 1 , further comprising:
forming one or more source/drain structures within at least one of the first portion, the second portion, or the third portion of the active region.

11 . The method of claim 1 , wherein the first to third interconnect structures are formed on a frontside of the substrate, the method further comprises:
forming a via structure on a backside of the substrate connected to at least one of the first portion, the second portion, or the third portion of the active region; and forming a fourth interconnect structure on the backside of the substrate connected to the via structure, wherein the fourth interconnect structure configured as an output node or a power rail.

12 . A semiconductor device, comprising:
an active region formed over a substrate and extending along a first lateral direction; a first interconnect structure extending along a second lateral direction and disposed over a first portion of the active region; a second interconnect structure extending along the second lateral direction and disposed over a second portion of the active region; a third interconnect structure extending along the second lateral direction and disposed over a third portion of the active region, wherein the first interconnect structure is disposed between the second and third interconnect structures; and a dielectric structure interposed between the first interconnect structure and the first portion of the active region.

13 . The semiconductor device of claim 12 , wherein the second lateral direction is perpendicular to the first lateral direction.

14 . The semiconductor device of claim 12 , further comprising:
a first gate structure extending along the second lateral direction and traversing across the active region, the first gate structure disposed between the second interconnect structure and the first interconnect structure; and a second gate structure extending along the second lateral direction and traversing across the active region, the second gate structure disposed between the first interconnect structure and the third interconnect structure.

15 . The semiconductor device of claim 12 , wherein:
the second portion of the active region comprises a first source/drain structure of a first transistor and the first portion of the active region comprises a second source/drain structure of the first transistor, the first portion of the active region comprises a third source/drain structure of a second transistor and the third portion of the active region comprises a fourth source/drain structure of the second transistor, and the second source/drain structure and the third source/drain structure merge as a common source/drain structure.

16 . The semiconductor device of claim 12 , further comprising:
a via structure disposed over and connected to the first interconnect structure; and a fourth interconnect structure disposed over and connected to the via structure, wherein the fourth interconnect structure extends along the first lateral direction and is configured at a power supply voltage or a fixed voltage.

17 . The semiconductor device of claim 12 , wherein the dielectric structure is a first dielectric structure, the semiconductor device further comprises:
a second dielectric structure interposed between at least one of:
the second interconnect structure and the second portion of the active region; or
the third interconnect structure and the third portion of the active region.

18 . A semiconductor device, comprising:
an active region formed over a substrate and extending along a first lateral direction, wherein a first portion of the active region comprises one of first source/drain structures of a first transistor and one of second source/drain structures of a second transistor merged as a common source/drain structure; a first gate structure extending along a second lateral direction and traversing across the active region; a second gate structure extending along the second lateral direction and traversing across the active region, wherein the first portion is interposed between the first gate structure and the second gate structure; a first interconnect structure extending along the second lateral direction and disposed between the first gate structure and the second gate structure; and a first dielectric structure interposed between the first interconnect structure and the first portion of the active region, wherein the first portion of the active region is electrically isolated from the first interconnect structure by the first dielectric structure.

19 . The semiconductor device of claim 18 , wherein:
the first dielectric structure is vertically interposed bet

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Lu Chih-Yu
• Chen Chih-Liang
• Wang Meng-Hsueh
• Lai Chih-Yu
• Chiu Shang Hsuan

Classifications

• H10W20/435

  Cross-sectional shapes or dispositions of interconnections · CPC title

• H10W20/427 Primary

  Power or ground buses · CPC title

• H10W20/42

  Vias, e.g. via plugs · CPC title

• H10W20/423 Primary

  Shielding layers · CPC title

• H10D84/834

  comprising FinFETs · CPC title