Display device

Patent metadata

Field	Value
Publication number	US-2025363936-A1
Application number	US-202519078286-A
Country	US
Kind code	A1
Filing date	Mar 13, 2025
Priority date	May 21, 2024
Publication date	Nov 27, 2025
Grant date	—

Abstract

A display device includes a display area including a pixel that emits light, and a scan driver that is configured to supply a scan signal to the pixel, and a non-display area surrounding the display area, extending in a first direction, and including a clock line that is configured to supply a clock signal to the scan driver. The scan driver includes a first gate driver configured to supply a first gate signal to the pixel, a second gate driver configured to supply a second gate signal and a third gate signal to the pixel, and a light emitting control driver configured to supply a light emitting signal to the pixel. The clock line is closest to the first gate driver in the scan driver among the first gate driver, the second gate driver, and the light emitting control driver.

First claim

What is claimed is:

1 . A display device comprising:
a display area including a pixel that emits light, and a scan driver that is configured to supply a scan signal to the pixel; and a non-display area surrounding the display area, extending in a first direction, and including a clock line that is configured to supply a clock signal to the scan driver, wherein the scan driver includes: a first gate driver configured to supply a first gate signal to the pixel; a second gate driver configured to supply a second gate signal and a third gate signal to the pixel; and a light emitting control driver configured to supply a light emitting signal to the pixel, and the clock line is closest to the first gate driver in the scan driver among the first gate driver, the second gate driver, and the light emitting control driver.

2 . The display device of claim 1 , wherein a length of each of the first gate driver, the second gate driver, and the light emitting control driver in a second direction intersecting the first direction is greater than a length of each of the first gate driver, the second gate driver, and the light emitting control driver in the first direction.

3 . The display device of claim 1 , wherein each of a width of the second gate driver in the first direction and a width of the light emitting control driver in the first direction is greater than a width of the first gate driver in the first direction.

4 . The display device of claim 1 , further comprising a connection line extending in a second direction intersecting the first direction and electrically connecting the clock line and the scan driver.

5 . The display device of claim 4 , wherein the clock line includes:
a write clock line configured to supply a clock signal to the first gate driver; a control clock line configured to supply a clock signal to the second gate driver; and a light emitting clock line configured to supply a clock signal to the light emitting control driver.

6 . The display device of claim 5 , wherein the write clock line is closest to the display area among the write clock line, the control clock line, and the light emitting clock line.

7 . The display device of claim 5 , wherein the connection line includes:
a first connection line electrically connecting the write clock line and the first gate driver; a second connection line electrically connecting the control clock line and the second gate driver; and a third connection line electrically connecting the light emitting clock line and the light emitting control driver.

8 . The display device of claim 7 , wherein the first gate driver includes a plurality of stages arranged in the first direction, and
the second connection line passes between stages adjacent to each other in the first direction.

9 . The display device of claim 8 , wherein the second gate driver includes a plurality of stages arranged in the first direction, and
the third connection line passes between the stages of the first gate driver adjacent to each other in the first direction and between stages of the second drivers adjacent to each other in the first direction.

10 . The display device of claim 1 , further comprising:
a start connection line disposed in the non-display area to supply a start signal; and a start line disposed in the display area and connected to the start connection line to supply the start signal to the scan driver.

11 . The display device of claim 10 , wherein the start line includes:
a first start line configured to supply a first start signal to the first gate driver; a second start line configured to supply a second start signal to the second gate driver; and a third start line configured to supply a third start signal to the light emitting control driver, and the start connection line includes: a first start connection line configured to supply the first start signal to the first start line; a second start connection line configured to supply the second start signal to the second start line; and a third start connection line configured to supply the third start signal to the third start line.

12 . The display device of claim 10 , wherein each of the first, second, and third start connection lines includes:
a first portion disposed on a first side of the non-display area including the clock line and extending in the first direction; a second portion connected to the first portion and extending in a second direction intersecting the first direction from a second side adjacent to the first side of the non-display area; and a third portion connected to the second portion and extending to the display area.

13 . The display device of claim 1 , wherein the scan driver includes a scan transistor disposed in a first active layer including a first material, and
the pixel includes a transistor disposed in a second active layer including a second material different from the first material.

14 . The display device of claim 13 , wherein the pixel includes:
a light emitting element; a first transistor supplying a driving current to the light emitting element; a second transistor supplying a data voltage to a first electrode of the first transistor; a third transistor electrically connecting a second electrode of the first transistor and a gate electrode of the first transistor; a fourth transistor configured to supply an initialization voltage to the gate electrode of the first transistor; a fifth transistor configured to supply a driving voltage to the first electrode of the first transistor; and a sixth transistor electrically connecting the second electrode of the first transistor and a first electrode of the light emitting element.

15 . The display device of claim 14 , wherein the first gate driver is configured to supply the first gate signal to a gate electrode of the second transistor,
the second gate driver is configured to supply the second gate signal to a gate electrode of the third transistor and the third gate signal to a gate electrode of the fourth transistor, and the light emitting control driver is configured to supply the light emitting signal to a gate electrode of each of the fifth and sixth transistors.

16 . An electronic device comprising:
a display device for providing an image, and wherein the display device comprises: a display area including a pixel that includes a transistor to emit light, and a scan driver that includes a scan transistor to supply a scan signal to the pixel; a non-display area surrounding the display area, extending in a first direction, and including a clock line that supplies a clock signal to the scan driver; a first active layer including a semiconductor area of the scan transistor; a first gate layer disposed on the first active layer and including a gate electrode of the scan transistor; a second gate layer disposed on the first gate layer; a first connection metal layer disposed on the second gate layer and including a gate low voltage line; a second connection metal layer disposed on the first connection metal layer and including a metal layer; a second active layer disposed on the second connection metal layer and including a semiconductor area of the transistor overlapping the metal layer; a third gate layer disposed on the second active layer and including a gate electrode of the transistor; and a first source metal layer disposed on the third gate layer and including the clock line.

17 . The electronic device of claim 16 , wherein the scan transistor and the transistor overlap in a thickness directio

Assignees

• Samsung Display Co Ltd

Inventors

• Jeon Joo Hee
• Kim Gun Hee
• Jang Sang Hee
• Jung Sun Young

Classifications

• G09G3/3233

  with pixel circuitry controlling the current through the light-emitting element · CPC title

• G09G3/3266 Primary

  Details of drivers for scan electrodes · CPC title

• G09G2310/0267

  Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays · CPC title

• G09G2330/021

  Power management, e.g. power saving · CPC title

• G09G2300/0426

  Layout of electrodes and connections · CPC title