Nonvolatile memory including intermediate buffer and input/output buffer and memory system including the nonvolatile memory

Patent metadata

Field	Value
Publication number	US-2025362808-A1
Application number	US-202519295952-A
Country	US
Kind code	A1
Filing date	Aug 11, 2025
Priority date	Sep 18, 2018
Publication date	Nov 27, 2025
Grant date	—

Abstract

According to one embodiment, there is provided a nonvolatile memory including a memory cell array, an input/output buffer, one or more intermediate buffers, and a control circuit. The memory cell array includes a plurality of pages. Each of the one or more intermediate buffers is electrically connected between the memory cell array and the input/output buffer. The control circuit is configured to store, in a first intermediate buffer, data read through sensing operation from a first page out of the plurality of pages in accordance with a first command that includes a sensing operation instruction and designation of the first intermediate buffer among the one or more intermediate buffers.

First claim

What is claimed is:

1 . A information processing system comprising:
a host system including:
a main memory; and
processor circuitry, and
a memory system connected with the host system via a bus, wherein the processor circuitry is configured to:
generate one or more read commands each specifying a logical address; and
transmit the one or more read commands to the memory system, and
the memory system includes:
a nonvolatile memory including a memory cell array, an input/output buffer, and a plurality of intermediate buffers each electrically connected between the memory cell array and the input/output buffer, the memory cell array including a plurality of pages, the plurality of pages including at least a first page and a second page, the second page being different from the first page, the plurality of intermediate buffers including at least a first intermediate buffer and a second intermediate buffer, the second intermediate buffer being different from the first intermediate buffer; and
a controller electrically connected to the nonvolatile memory and configured to:
in response to receiving the one or more read commands, based on the logical address specified in each of the one or more read commands, identify the first page and the second page respectively as a read target page;
by transmitting, to the nonvolatile memory, a first command sequence that includes a first sensing operation instruction, designation of the first intermediate buffer, and designation of the first page, instruct the nonvolatile memory to store first data read through a sensing operation from the first page into the first intermediate buffer; and
by transmitting, to the nonvolatile memory, a second command sequence that includes a second sensing operation instruction, designation of the second intermediate buffer, and designation of the second page, instruct the nonvolatile memory to store second data read through a sensing operation from the second page into the second intermediate buffer.

2 . The information processing system according to claim 1 , wherein
a period during which the first data is in the first intermediate buffer and a period during which the second data is in the second intermediate buffer overlap each other.

3 . The information processing system according to claim 1 , wherein
the controller is further configured to:
by transmitting, to the nonvolatile memory, a third command sequence that includes a transfer instruction and designation of the first intermediate buffer, instruct the nonvolatile memory to transfer at least first part of the first data stored in the first intermediate buffer to the input/output buffer.

4 . The information processing system according to claim 3 , wherein
the controller is further configured to:
by transmitting, to the nonvolatile memory, a fourth command sequence that includes an output instruction, instruct the nonvolatile memory to output the first part of the first data from the input/output buffer; and
transmit the first part of the first data to the host system, and
the processor circuitry of the host system is further configured to:
store the first part of the first data, which has been received from the memory system, into the main memory.

5 . The information processing system according to claim 4 , wherein
the controller is further configured to:
by transmitting, to the nonvolatile memory, a fifth command sequence that includes a transfer instruction and designation of the second intermediate buffer, instruct the nonvolatile memory to transfer at least first part of the second data stored in the second intermediate buffer to the input/output buffer.

6 . The information processing system according to claim 5 , wherein
the controller is further configured to:
by transmitting, to the nonvolatile memory, a sixth command sequence that includes an output instruction, instruct the nonvolatile memory to output the first part of the second data from the input/output buffer.

7 . The information processing system according to claim 6 , wherein
the controller is further configured to:
without transmitting the first sensing operation instruction again, by transmitting, to the nonvolatile memory, a seventh command sequence that includes a transfer instruction and designation of the first intermediate buffer, instruct the nonvolatile memory to transfer second part of the first data stored in the first intermediate buffer to the input/output buffer; and
without transmitting the second sensing operation instruction again, by transmitting, to the nonvolatile memory, an eighth command sequence that includes a transfer instruction and designation of the second intermediate buffer, instruct the nonvolatile memory to transfer second part of the second data stored in the second intermediate buffer to the input/output buffer.

8 . The information processing system according to claim 1 , wherein
the controller is further configured to use each of the plurality of intermediate buffers in a program operation performed for each of the plurality of pages.

9 . The information processing system according to claim 1 , wherein
the nonvolatile memory further includes a sense amplifier circuit, wherein one of the plurality of intermediate buffers is electrically connected to the sense amplifier circuit and to the input/output buffer.

10 . The information processing system according to claim 1 , wherein
the nonvolatile memory further includes an input/output interface, wherein the input/output buffer is electrically connected to the input/output interface and to one of the plurality of intermediate buffers.

11 . A information processing system comprising:
a host system including:
a main memory; and
processor circuitry, and
a memory system connected with the host system via a bus, wherein the processor circuitry is configured to:
generate one or more read commands each specifying a logical address; and
transmit the one or more read commands to the memory system,
the memory system includes:
a nonvolatile memory including a memory cell array, an input/output buffer, and one or more intermediate buffers each electrically connected between the memory cell array and the input/output buffer, the memory cell array including a plurality of pages, the plurality of pages including at least a first page and a second page, the second page being different from the first page, the one or more intermediate buffers including at least a first intermediate buffer; and
a controller electrically connected to the nonvolatile memory and configured to:
in response to receiving the one or more read commands, based on the logical address specified in each of the one or more read commands, identify the first page and the second page respectively as a read target page;
by transmitting, to the nonvolatile memory, a first command sequence that includes a first sensing operation instruction, designation of the first page, and designation of the first intermediate buffer, instruct the nonvolatile memory to store first data read through a sensing operation from the first page into the first intermediate buffer;
by transmitting, to the nonvolatile memory, a second command sequence that includes a second sensing operation instruction, designation of the second page, but does not include designation of any of the intermediate buffers, instruct the nonvolatile memory to store second data read through a sensing operation from the second page into the input/output buffer;
by transmitting, to the nonvolatile memory, a third command sequence that includes an output instruction, instruct the nonvolatile memory to output the second data from the

Assignees

• Kioxia Corp

Inventors

• Kojima Yoshihisa
• Shirakawa Masanobu
• Iwasaki Kiyotaka

Classifications

• G06F3/0656

  Data buffering arrangements · CPC title

• G06F3/0659

  Command handling arrangements, e.g. command buffers, queues, command scheduling · CPC title

• G06F3/0679

  Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP] · CPC title

• G06F3/0611 Primary

  in relation to response time · CPC title