Optical logic and quantum-limited signal processing in large-scale optoelectronic circuits

Patent metadata

Field	Value
Publication number	US-2025362561-A1
Application number	US-202519214313-A
Country	US
Kind code	A1
Filing date	May 21, 2025
Priority date	May 22, 2024
Publication date	Nov 27, 2025
Grant date	—

Abstract

A new architecture for a photoelectric logic gate is disclosed. This architecture is energy-efficient, realizes a strong optical nonlinearity, and can be directly realized in modern photonics foundries without process modifications, enabling immediate application to current-day photonic systems. The new architecture utilizes the integration of current onto the intrinsic capacitance of the optical modulator.

First claim

What is claimed is:

1 . A photoelectric gate, comprising:
a first port in communication with a first photodiode to receive a control signal; and an optical modulator to modulate an input signal to form an output signal; wherein photogenerated current from the first photodiode is integrated onto an intrinsic capacitance of the optical modulator to control a state of the optical modulator.

2 . The photoelectric gate of claim 1 , wherein the control signal and the input signal are different wavelengths to allow the photoelectric gate to serve as a wavelength converter.

3 . The photoelectric gate of claim 1 , wherein the first photodiode comprises a single photon avalanche diode (SPAD) such that a single photon incident on the first photodiode is detected at the output signal.

4 . The photoelectric gate of claim 1 , wherein the intrinsic capacitance and a quality factor of the optical modulator are selected such that a single photon incident on the first photodiode is detected at the output signal.

5 . The photoelectric gate of claim 1 , wherein the optical modulator is a Mach-Zehnder modulator, tunable directional coupler, microring, microdisk, pn-doped silicon modulator or photonic crystal modulator.

6 . The photoelectric gate of claim 1 , further comprising a second port in communication with a second photodiode to receive a bias or reset signal, wherein photogenerated current from the second photodiode is subtracted from the photogenerated current from the first photodiode prior to being integrated onto the intrinsic capacitance of the optical modulator.

7 . The photoelectric gate of claim 6 , wherein the photoelectric gate serves as a comparator that compares the control signal to the bias or reset signal and wherein the output signal indicates a result on the comparison.

8 . An optical inverter comprising the photoelectric gate of claim 6 .

9 . The optical inverter of claim 8 , wherein the optical modulator is optically biased such that when it charges up to a maximum voltage, the input signal is extinguished such that the output signal is not present.

10 . The optical inverter of claim 8 , wherein the bias or reset signal is set to a fixed bias optical power.

11 . An optical AND gate, comprising:
the optical inverter of claim 8 ; and a second optoelectronic a gate, wherein the second optoelectronic gate comprises:
a second optical modulator to modulate a second input signal to form a second output signal;
a third port in communication with a third photodiode to receive a second control signal;
a fourth port in communication with a fourth photodiode to receive the output signal from the optical inverter, wherein photogenerated current from the fourth photodiode is subtracted from the photogenerated current from the third photodiode and then integrated onto an intrinsic capacitance of the second optical modulator to control a state of the second optical modulator;
wherein the input signal to the optical inverter and the second optoelectronic gate is a pump; and wherein inputs to the first port of the optical inverter and the third port of the second optoelectronic gate comprise the inputs to the optical AND gate; and the output signal from the second optoelectronic gate comprises an output of the optical AND gate.

12 . An optical NAND gate, comprising the optical AND gate of claim 11 , wherein an output of the second optoelectronic gate serves as an input to a second optical inverter.

13 . An optical memory, comprising:
the photoelectric gate of claim 6 ; and a switch disposed between the photodiodes and the optical modulator, to isolate the optical modulator from the photodiodes in a memory storage mode and enable passage of current in a memory writing mode.

14 . The optical memory of claim 13 , further comprising a capacitor in parallel with the intrinsic capacitance of the optical modulator to retain the state of the optical modulator.

15 . An optical neural network, comprising:
the photoelectric gate of claim 6 ;
wherein the first port in communication receives one of two signals obtained by homodyne mixing of an activation and weight signal; and
the second port receives a second of the two signals obtained by the homodyne mixing of the activation and weight signal.

16 . The optical neural network of claim 15 , wherein the optical modulator is operated in a linear regime.

17 . The optical neural network of claim 15 , wherein the optical modulator is operated in a non-linear regime to apply an activation function to the input signal.

18 . A photoelectric gate, comprising:
the photoelectric gate of claim 6 ; and
an optical tap in communication with the output signal, where part of the output signal is fed back to the first port or the second port.

19 . The photoelectric gate of claim 18 , wherein the first port is in communication with a control signal and the part of the output signal is fed back to the second port.

20 . The photoelectric gate of claim 18 , wherein the second port is in communication with a control signal and the part of the output signal is fed back to the first port.

21 . An optical Digital to Analog converter (DAC), comprising:
a first stage, comprising:
a plurality of photoelectric gates, wherein each photoelectric gate comprises:
a first port in communication with a first photodiode to receive a control signal, indicative of a digital value;
a second port in communication with a second photodiode to receive a bias signal; and
an optical modulator to modulate an input signal to form an output signal; wherein photogenerated current from the second photodiode is subtracted from the photogenerated current from the first photodiode prior to being integrated onto an intrinsic capacitance of the optical modulator to control a state of the optical modulator, wherein the optical modulator affects one wavelength;
wherein a plurality of pump wavelengths are incoherently combined into a single bus waveguide through a binary tree of 2×1 splitters and serve as the input signal to the first stage;
and a final stage, comprising:
a photoelectric gate comprising:
a first port in communication with a first final stage photodiode to receive the output signal from the first stage;
a second port in communication with a second final stage photodiode to receive the bias signal; and
a final stage optical modulator to modulate a second input signal to form a second output signal; wherein photogenerated current from the second final stage photodiode is subtracted from the photogenerated current from the first final stage photodiode prior to being integrated onto the intrinsic capacitance of the final stage optical modulator to control a state of the final stage optical modulator, and wherein the second output signal represents an analog representation of the digital values.

22 . A photoelectric gate, comprising:
an optical modulator to modulate an input signal to form an output signal; a digital logic gate having an input, and an output in communication with the optical modulator;
a first port in communication with a first photodiode to receive a control signal; and
a second port in communication with a second photodiode to receive a reset signal, wherein photogenerated current from the second photodiode is subtracted from the photogenerated current from the first photodiode prior to being integrated onto an input capacitance at the input of the digital logic gate disposed b

Assignees

• Massachusetts Inst Technology
• Ntt Research Inc

Inventors

• Bandyopadhyay Saumil
• Hamerly Ryan
• Englund Dirk

Classifications

• G02F3/00 Primary

  Optical logic elements; Optical bistable devices · CPC title

• G06N3/0675

  using electro-optical, acousto-optical or opto-electronic means · CPC title

• G02F7/00 Primary

  Optical analogue/digital converters · CPC title