Semiconductor device structure

Patent metadata

Field	Value
Publication number	US-2025359217-A1
Application number	US-202519285997-A
Country	US
Kind code	A1
Filing date	Jul 30, 2025
Priority date	Mar 10, 2022
Publication date	Nov 20, 2025
Grant date	—

Abstract

A semiconductor device structure includes first nanostructures and second nanostructures over a substrate. The semiconductor device structure also includes a first metal gate layer surrounding the first nanostructures. The semiconductor device structure further includes a second metal gate layer surrounding the second nanostructures and over the first metal gate layer. The first metal gate layer comprises N-work-function metal, and the second metal gate layer comprises P-work-function metal.

First claim

What is claimed is:

1 . A semiconductor device structure, comprising:
first nanostructures and second nanostructures over a substrate; a first metal gate layer surrounding the first nanostructures; a second metal gate layer surrounding the second nanostructures and over the first metal gate layer, wherein the first metal gate layer comprises N-work-function metal, and the second metal gate layer comprises P-work-function metal.

2 . The semiconductor device structure as claimed in claim 1 , wherein a top surface of the second metal gate layer is higher than a top surface of the first metal gate layer.

3 . The semiconductor device structure as claimed in claim 1 , further comprising:
first spacer layers over opposite sides of the first metal gate layer over the first nanostructures; second spacer layers over opposite sides of the first spacer layers, wherein the top surface of the first metal gate layer is lower than top surfaces of the first spacer layers.

4 . The semiconductor device structure as claimed in claim 3 , further comprising:
a cap layer over the second metal gate layer between the second spacer layers.

5 . The semiconductor device structure as claimed in claim 3 , wherein the second metal gate layer is directly above the first spacer layers.

6 . The semiconductor device structure as claimed in claim 1 , wherein the first metal gate layer is narrower than the second metal gate layer over the first nanostructures.

7 . The semiconductor device structure as claimed in claim 1 , further comprising:
a first glue layer surrounding the first metal gate layer, wherein a top surface of the first glue layer is substantially level with the top surface of the first metal gate layer.

8 . A semiconductor device structure, comprising:
first nanostructures over a first region of a substrate; second nanostructures over a second region of the substrate; a first metal gate layer surrounding the first nanostructures; a second metal gate layer surrounding the second nanostructures and over the first metal gate layer, wherein a first top surface of the second metal gate layer in the first region of the substrate is higher than a second top surface of the second metal gate layer in the second region of the substrate.

9 . The semiconductor device structure as claimed in claim 8 , further comprising:
a first glue layer between the first metal gate layer and the second metal gate layer.

10 . The semiconductor device structure as claimed in claim 9 , wherein the first metal gate layer is surrounded by the first glue layer.

11 . The semiconductor device structure as claimed in claim 9 , further comprising:
a second glue layer over the second metal gate layer.

12 . The semiconductor device structure as claimed in claim 11 , wherein a first bottom surface of the second glue layer in the first region of the substrate is higher than a second bottom surface of the second glue layer in the second region of the substrate.

13 . The semiconductor device structure as claimed in claim 11 , wherein a seam is in the second glue layer.

14 . A semiconductor device structure, comprising:
first nanostructures over a first region of a substrate; second nanostructures over a second region of the substrate; a first metal gate layer surrounding the first nanostructures; a second metal gate layer surrounding the second nanostructures and over the first metal gate layer, wherein a first bottommost surface of the second metal gate layer in the first region of the substrate is higher than a second bottommost surface of the second metal gate layer in the second region of the substrate.

15 . The semiconductor device structure as claimed in claim 14 , further comprising:
a fin isolation structure between the first region of the substrate and the second region of the substrate.

16 . The semiconductor device structure as claimed in claim 15 , wherein a portion of the first metal gate layer extends on a top surface of the fin isolation structure.

17 . The semiconductor device structure as claimed in claim 16 , wherein a first portion of the second metal gate layer extends on the top surface of the fin isolation structure.

18 . The semiconductor device structure as claimed in claim 17 , wherein a second portion of the second metal gate layer extends on the portion of the first metal gate layer.

19 . The semiconductor device structure as claimed in claim 18 , wherein the first portion and the second portion of the second metal gate layer forms a stepped profile directly over the top surface of the fin isolation structure.

20 . The semiconductor device structure as claimed in claim 15 , further comprising:
a dielectric liner surrounding the fin isolation structure.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Yang Wen-Yao
• Chen Chia-Wei
• Hsu Wei-Cheng
• Hung Jo-Chun
• Chan Yung-Hsiang
• Chen Hui-Chi
• Lin Yen-Ta
• Yeh Te-Fu
• Wu Yun-Chen
• Chen Yen-Ju
• Sun Chih-Ming

Classifications

• H10P50/642

  Chemical etching · CPC title

• H10D84/0158

  the components including FinFETs · CPC title

• H10D84/038

  using silicon technology, e.g. SiGe · CPC title

• H10D30/6735

  having gates fully surrounding the channels, e.g. gate-all-around · CPC title

• H10D30/797

  being in source or drain regions, e.g. SiGe source or drain · CPC title