Insulating film, method for manufacturing semiconductor device, and semiconductor device

Patent metadata

Field	Value
Publication number	US-2025359185-A1
Application number	US-202519280392-A
Country	US
Kind code	A1
Filing date	Jul 25, 2025
Priority date	Apr 6, 2012
Publication date	Nov 20, 2025
Grant date	—

Abstract

In a semiconductor device including a transistor including an oxide semiconductor film and a protective film over the transistor, an oxide insulating film containing oxygen in excess of the stoichiometric composition is formed as the protective film under the following conditions: a substrate placed in a treatment chamber evacuated to a vacuum level is held at a temperature higher than or equal to 180° C. and lower than or equal to 260° C.; a source gas is introduced into the treatment chamber so that the pressure in the treatment chamber is set to be higher than or equal to 100 Pa and lower than or equal to 250 Pa; and a high-frequency power higher than or equal to 0.17 W/cm 2 and lower than or equal to 0.5 W/cm 2 is supplied to an electrode provided in the treatment chamber.

First claim

1 . (canceled)

2 . A semiconductor device comprising:
a first transistor having a first channel formation region comprising silicon; a second transistor having a second channel formation region provided in an oxide semiconductor layer; a first conductive layer over the first channel formation region, the first conductive layer having a region configured to be a gate of the first transistor; a second conductive layer over the first conductive layer; a third conductive layer over the oxide semiconductor layer, the third conductive layer electrically connected to one of a source and a drain of the second transistor; and a fourth conductive layer over the oxide semiconductor layer, the fourth conductive layer electrically connected to the other of the source and the drain of the second transistor, wherein the one of the source and the drain of the second transistor is electrically connected to the gate of the first transistor through the third conductive layer and the second conductive layer, and wherein the fourth conductive layer has a region overlapping at least one of a source and a drain of the first transistor.

3 . The semiconductor device according to claim 2 , wherein the first channel formation region comprises polycrystalline silicon.

4 . The semiconductor device according to claim 2 , wherein the oxide semiconductor layer comprises indium, gallium, and zinc.

5 . The semiconductor device according to claim 2 , wherein the oxide semiconductor layer is provided over the first conductive layer.

6 . A semiconductor device comprising:
a first transistor having a first channel formation region comprising silicon; a second transistor having a second channel formation region provided in an oxide semiconductor layer; a first conductive layer over the first channel formation region, the first conductive layer having a region configured to be a gate of the first transistor; a first insulating layer over the first conductive layer; a second conductive layer over the first insulating layer; a third conductive layer over the oxide semiconductor layer, the third conductive layer electrically connected to one of a source and a drain of the second transistor; and a fourth conductive layer over the oxide semiconductor layer, the fourth conductive layer electrically connected to the other of the source and the drain of the second transistor, wherein the one of the source and the drain of the second transistor is electrically connected to the gate of the first transistor through the third conductive layer and the second conductive layer, and wherein the fourth conductive layer has a region overlapping at least one of a source and a drain of the first transistor.

7 . The semiconductor device according to claim 6 , wherein the first channel formation region comprises polycrystalline silicon.

8 . The semiconductor device according to claim 6 , wherein the oxide semiconductor layer comprises indium, gallium, and zinc.

9 . The semiconductor device according to claim 6 , wherein the oxide semiconductor layer is provided over the first insulating layer.

10 . A semiconductor device comprising:
a first transistor having a first channel formation region comprising silicon; a second transistor having a second channel formation region provided in an oxide semiconductor layer; a third transistor having a third channel formation region comprising silicon; a fourth transistor having a fourth channel formation region comprising silicon; a first conductive layer over the first channel formation region, the first conductive layer having a region configured to be a gate of the first transistor; a second conductive layer over the first conductive layer; a third conductive layer over the oxide semiconductor layer, the third conductive layer electrically connected to one of a source and a drain of the second transistor; and a fourth conductive layer over the oxide semiconductor layer, the fourth conductive layer electrically connected to the other of the source and the drain of the second transistor, wherein the one of the source and the drain of the second transistor is electrically connected to the gate of the first transistor through the third conductive layer and the second conductive layer, wherein the fourth conductive layer has a region overlapping at least one of a source and a drain of the first transistor, wherein one of a source and a drain of the third transistor is electrically connected to the oxide semiconductor layer, and wherein the other of the source and the drain of the third transistor is electrically connected to one of a source and a drain of the fourth transistor.

11 . The semiconductor device according to claim 10 , wherein each of the first channel formation region, the third channel formation region, and the fourth channel formation region comprises polycrystalline silicon.

12 . The semiconductor device according to claim 10 , wherein the oxide semiconductor layer comprises indium, gallium, and zinc.

13 . The semiconductor device according to claim 10 , wherein the oxide semiconductor layer is provided over the first conductive layer.

14 . The semiconductor device according to claim 10 , wherein the third transistor and the fourth transistor are p-channel transistors.

Assignees

• Semiconductor Energy Lab

Inventors

• Okazaki Kenichi
• Sasaki Toshinari
• Yokoyama Shuhei
• Hamochi Takashi

Classifications

• H10D30/6757

  characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715) · CPC title

• H10D30/6734

  having gate electrodes arranged on both top and bottom sides of the channel, e.g. dual-gate TFTs · CPC title

• H10D30/6704

  having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device · CPC title

• H10D30/031

  of thin-film transistors [TFT] · CPC title

• H10D30/60

  Insulated-gate field-effect transistors [IGFET] (H10D30/40 takes precedence) · CPC title