Display device, method of manufacturing the same, and electronic device

US2025344577A1 · US · A1

Patent metadata
FieldValue
Publication numberUS-2025344577-A1
Application numberUS-202519091293-A
CountryUS
Kind codeA1
Filing dateMar 26, 2025
Priority dateMay 3, 2024
Publication dateNov 6, 2025
Grant date

How to read this patent

A practical reading order for non-experts. Skip the full description unless you need deep technical detail.

  1. Title

    What the patent document calls the invention.

  2. Abstract

    A short plain-language summary of the technical disclosure.

  3. Assignees and inventors

    Who owns or filed the patent and who is credited as inventor.

  4. Key dates

    Filing, priority, publication, and grant dates set the timeline.

  5. First independent claim

    The legal scope of protection — read this for what is actually claimed.

  6. CPC / IPC classifications

    Technology tags used to group this patent with similar filings.

  7. Citations and related patents

    Prior art links and similar publications in this corpus.

Abstract

Official abstract text for this publication.

A display device includes a circuit element layer including a thin film transistor, a pixel electrode disposed on the circuit element layer, electrically connected to the thin film transistor, and including a central portion, an outer portion outside the central portion, and a first emission portion between the central portion and the outer portion, an insulating pattern disposed between the circuit element layer and the central portion of the pixel electrode, a pixel defining pattern disposed on the central portion of the pixel electrode, a pixel defining layer disposed on the circuit element layer and the pixel electrode, covering the outer portion of the pixel electrode, and exposing the first emission portion of the pixel electrode, an intermediate layer disposed on the pixel electrode, the pixel defining pattern, and the pixel defining layer and including an emission layer, and a common electrode disposed on the intermediate layer.

First claim

Opening claim text (preview).

What is claimed is: 1 . A display device comprising: a circuit element layer including a thin film transistor; a pixel electrode disposed on the circuit element layer, electrically connected to the thin film transistor, and including a central portion, an outer portion outside the central portion in a plan view, and a first emission portion between the central portion and the outer portion; an insulating pattern disposed between the circuit element layer and the central portion of the pixel electrode; a pixel defining pattern disposed on the central portion of the pixel electrode; a pixel defining layer disposed on the circuit element layer and the pixel electrode, covering the outer portion of the pixel electrode, and exposing the first emission portion of the pixel electrode; an intermediate layer disposed on the pixel electrode, the pixel defining pattern, and the pixel defining layer, and including an emission layer; and a common electrode disposed on the intermediate layer. 2 . The display device of claim 1 , wherein the pixel defining pattern covers the central portion of the pixel electrode and exposes the first emission portion of the pixel electrode. 3 . The display device of claim 1 , wherein in a plan view, each of the insulating pattern and the pixel defining pattern has an island pattern shape, and the pixel defining layer surrounds the central portion of the pixel electrode and the first emission portion of the pixel electrode. 4 . The display device of claim 1 , wherein in a plan view, the first emission portion surrounds the central portion, and the outer portion surrounds the first emission portion. 5 . The display device of claim 1 , wherein the central portion of the pixel electrode is spaced apart from the intermediate layer with the pixel defining pattern interposed between the central portion of the pixel electrode and the intermediate layer, the outer portion of the pixel electrode is spaced apart from the intermediate layer with the pixel defining layer interposed between the outer portion of the pixel electrode and the intermediate layer, and the first emission portion of the pixel electrode contacts the intermediate layer. 6 . The display device of claim 1 , wherein in a plan view, the pixel defining layer is spaced apart from the pixel defining pattern and surrounds the pixel defining pattern. 7 . The display device of claim 1 , wherein in a plan view the first emission portion of the pixel electrode is located outside the insulating pattern, and the insulating pattern includes a flat portion and an inclined portion outside the flat portion. 8 . The display device of claim 7 , wherein the pixel electrode further includes a second emission portion between the central portion and the first emission portion, the central portion of the pixel electrode is located on the flat portion of the insulating pattern, and the second emission portion of the pixel electrode is located on the inclined portion of the insulating pattern. 9 . The display device of claim 8 , wherein the second emission portion of the pixel electrode is inclined along an inclined surface of the inclined portion of the insulating pattern and contacts the intermediate layer. 10 . The display device of claim 8 , wherein the pixel defining pattern covers the central portion of the pixel electrode and exposes the second emission portion of the pixel electrode. 11 . The display device of claim 8 , wherein in a plan view, the second emission portion surrounds the central portion, and the first emission portion surrounds the second emission portion. 12 . The display device of claim 1 , further comprising: an insulating layer disposed between the circuit element layer and the outer portion of the pixel electrode and between the circuit element layer and the pixel defining layer, and including a flat portion and an inclined portion outside the flat portion in a plan view, and wherein the first emission portion of the pixel electrode is located between the insulating pattern and the insulating layer. 13 . The display device of claim 12 , wherein in a plan view, each of the insulating pattern and the pixel defining pattern has an island pattern shape, and each of the insulating layer and the pixel defining layer surrounds the central portion of the pixel electrode and the first emission portion of the pixel electrode. 14 . The display device of claim 12 , wherein in a plan view, the insulating layer is spaced apart from the insulating pattern and surrounds the insulating pattern. 15 . The display device of claim 12 , wherein the pixel electrode further includes a third emission portion between the outer portion and the first emission portion, the outer portion of the pixel electrode is located on the flat portion of the insulating layer, and the third emission portion of the pixel electrode is located on the inclined portion of the insulating layer. 16 . The display device of claim 15 , wherein the third emission portion of the pixel electrode is inclined along an inclined surface of the inclined portion of the insulating layer and contacts the intermediate layer. 17 . The display device of claim 15 , wherein the pixel defining layer exposes the third emission portion of the pixel electrode. 18 . The display device of claim 15 , wherein in a plan view, the third emission portion surrounds the first emission portion, and the outer portion surrounds the third emission portion. 19 . The display device of claim 1 , further comprising: an encapsulation layer disposed on the common electrode; a light blocking layer disposed on the encapsulation layer in a cross-sectional view and overlapping the pixel defining layer in a plan view; a light blocking pattern disposed on the encapsulation layer in a cross-sectional view and overlapping the pixel defining pattern in a plan view; and a color filter disposed on the encapsulation layer in a cross-sectional view and overlapping the pixel electrode in a plan view. 20 . A method of manufacturing a display device, the method comprising: forming, on a substrate, a circuit element layer including a thin film transistor; forming an insulating pattern on the circuit element layer; forming, on the circuit element layer, a pixel electrode including a central portion on the insulating pattern, an outer portion outside the central portion in a plan view, and an emission portion between the central portion and the outer portion; forming a preliminary insulating layer on the circuit element layer and the pixel electrode; forming a pixel defining pattern on the central portion of the pixel electrode and a pixel defining layer covering the outer portion of the pixel electrode and exposing the emission portion of the pixel electrode by patterning the preliminary insulating layer; forming, on the pixel electrode, the pixel defining pattern, and the pixel defining layer, an intermediate layer including an emission layer; and forming a common electrode on the intermediate layer. 21 . An electronic device comprising: a display device; and a power supply configured to provide power to the display device, wherein the display device comprises: a circuit element layer including a thin film transistor; a pixel electrode disposed on the circuit element layer, electrically connected to the thin film transistor, and including a central portion, an outer portion outside the central portion in a plan view, and a f

Assignees

Inventors

Classifications

  • Package configurations · CPC title

  • Manufacture or treatment · CPC title

  • H10K59/38Primary

    comprising colour filters or colour changing media [CCM] · CPC title

  • Encapsulations · CPC title

  • comprising light absorbing layers, e.g. black layers · CPC title

Patent family

Related publications grouped by family.

External sources

Frequently asked questions

Answers are generated from the same data shown on this page.

What does patent US2025344577A1 cover?
A display device includes a circuit element layer including a thin film transistor, a pixel electrode disposed on the circuit element layer, electrically connected to the thin film transistor, and including a central portion, an outer portion outside the central portion, and a first emission portion between the central portion and the outer portion, an insulating pattern disposed between the ci…
Who is the assignee on this patent?
Samsung Display Co Ltd
What technology area does this patent fall under?
Primary CPC classification H10K59/38. Mapped technology areas include Electricity.
When was this patent published?
Publication date Thu Nov 06 2025 00:00:00 GMT+0000 (Coordinated Universal Time) (A1). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).