Semiconductor device and manufacturing method thereof

Patent metadata

Field	Value
Publication number	US-2025344441-A1
Application number	US-202519269088-A
Country	US
Kind code	A1
Filing date	Jul 15, 2025
Priority date	Oct 16, 2009
Publication date	Nov 6, 2025
Grant date	—

Abstract

An object is to reduce leakage current and parasitic capacitance of a transistor used for an LSI, a CPU, or a memory. A semiconductor integrated circuit such as an LSI, a CPU, or a memory is manufactured using a thin film transistor in which a channel formation region is formed using an oxide semiconductor which becomes an intrinsic or substantially intrinsic semiconductor by removing impurities which serve as electron donors (donors) from the oxide semiconductor and has larger energy gap than that of a silicon semiconductor. With use of a thin film transistor using a highly purified oxide semiconductor layer with sufficiently reduced hydrogen concentration, a semiconductor device with low power consumption due to leakage current can be realized.

First claim

1 . (canceled)

2 . A semiconductor device comprising:
a first transistor comprising:
a first oxide semiconductor layer;
a first gate electrode layer over the first oxide semiconductor layer; and
a first source electrode layer and a first drain electrode layer over and in contact with a top surface of the first oxide semiconductor layer,
a second transistor comprising:
a second oxide semiconductor layer;
a second gate electrode layer over the second oxide semiconductor layer; and
a second source electrode layer and a second drain electrode layer over and in contact with a top surface of the second oxide semiconductor layer, and
a first electrode layer overlaps with a channel formation region of the first oxide semiconductor layer with an insulating layer therebetween on a lower side of the first oxide semiconductor layer, wherein no conductive layer overlaps a channel formation region of the second oxide semiconductor layer on a lower side of the second oxide semiconductor layer, wherein one of the first source electrode layer and the first drain electrode layer is in contact with a second electrode layer positioned on the same plane as the first electrode layer, wherein the other of the first source electrode layer and the first drain electrode layer comprises a region overlapping with the first electrode layer, wherein a channel length of the first transistor is longer than a channel length of the second transistor, wherein each of the first oxide semiconductor layer and the second oxide semiconductor layer comprises indium, gallium, and zinc, and wherein the insulating layer comprises a first insulating layer and a second insulating layer over the first insulating layer.

3 . A semiconductor device comprising:
a first transistor comprising:
a first oxide semiconductor layer;
a first gate electrode layer over the first oxide semiconductor layer; and
a first source electrode layer and a first drain electrode layer over and in contact with a top surface of the first oxide semiconductor layer,
a second transistor comprising:
a second oxide semiconductor layer;
a second gate electrode layer over the second oxide semiconductor layer; and
a second source electrode layer and a second drain electrode layer over and in contact with a top surface of the second oxide semiconductor layer, and
a first electrode layer overlaps with a channel formation region of the first oxide semiconductor layer with an insulating layer therebetween on a lower side of the first oxide semiconductor layer, wherein no conductive layer overlaps a channel formation region of the second oxide semiconductor layer on a lower side of the second oxide semiconductor layer, wherein one of the first source electrode layer and the first drain electrode layer is in contact with a second electrode layer positioned on the same plane as the first electrode layer, wherein the other of the first source electrode layer and the first drain electrode layer comprises a region overlapping with the first electrode layer, wherein a channel length of the first transistor is longer than a channel length of the second transistor, wherein each of the first oxide semiconductor layer and the second oxide semiconductor layer comprises indium, gallium, and zinc, wherein the insulating layer comprises a first insulating layer and a second insulating layer over the first insulating layer, and wherein the first gate electrode layer and the second gate electrode layer comprise the same materials and stacked-layer structures comprising molybdenum, titanium, chromium, tantalum, tungsten, aluminum, or copper.

4 . A semiconductor device comprising:
a first transistor comprising:
a first oxide semiconductor layer; and
a first gate electrode layer over the first oxide semiconductor layer,
a second transistor comprising:
a second oxide semiconductor layer; and
a second gate electrode layer over the second oxide semiconductor layer, and
a first electrode layer overlaps with a channel formation region of the first oxide semiconductor layer with an insulating layer therebetween on a lower side of the first oxide semiconductor layer, wherein no conductive layer overlaps a channel formation region of the second oxide semiconductor layer on a lower side of the second oxide semiconductor layer, wherein a channel length of the first transistor is longer than a channel length of the second transistor, wherein each of the first oxide semiconductor layer and the second oxide semiconductor layer comprises indium, gallium, and zinc, wherein the insulating layer comprises a first insulating layer and a second insulating layer over the first insulating layer, and wherein the first gate electrode layer and the second gate electrode layer comprise the same materials and stacked-layer structures comprising molybdenum, titanium, chromium, tantalum, tungsten, aluminum, or copper.

Assignees

• Semiconductor Energy Lab

Inventors

• Yamazaki Shunpei
• Koyama Jun
• Miyake Hiroyuki
• Takahashi Kei
• Toyotaka Kouhei
• Tsubuku Masashi
• Noda Kosei
• Kuwabara Hideaki

Classifications

• H10W44/248

  for antennas · CPC title

• H10W44/20

  at high-frequency [HF] or radio frequency [RF] · CPC title

• H02M3/07

  using capacitors charged and discharged alternately by semiconductor devices with control electrode {, e.g. charge pumps} · CPC title

• G11C19/28

  using semiconductor elements (G11C19/14, G11C19/36 take precedence) · CPC title

• G11C7/00

  Arrangements for writing information into, or reading information out from, a digital store (G11C5/00 takes precedence; auxiliary circuits for stores using semiconductor devices G11C11/4063, G11C11/413) · CPC title