Recovery method, storage device, and computing system

Patent metadata

Field	Value
Publication number	US-2025341973-A1
Application number	US-202519269187-A
Country	US
Kind code	A1
Filing date	Jul 15, 2025
Priority date	Feb 3, 2023
Publication date	Nov 6, 2025
Grant date	—

Abstract

A storage device according to an embodiment includes: a first memory that receives and stores a plurality of data packets including first tokens and data chunks corresponding to a plurality of storage devices from the plurality of storage devices; a direct memory access (DMA) engine that performs integrity verification using the first tokens of the plurality of data packets and generates a recovered data chunk using the data chunks of the plurality of data packets; and a second memory that stores the recovered data chunk.

First claim

1 .- 20 . (canceled)

21 . A storage system, comprising:
a first storage device configured to output a first data packet including a first token and a first data chunk, a second storage device configured to output a second data packet including a second token and a second data chunk, and a third storage device configured to receive the first data packet and the second data packet, perform integrity verification using the first token and the second token, and generate a recovered data chunk using the first data chunk and the second data chunk, wherein the recovered data chunk corresponds to a data chunk having an error.

22 . The storage system of claim 21 , wherein the first token and the second token are generated using a random function.

23 . The storage system of claim 21 , wherein the first token is generated based on an identifier and a logical block address (LBA) of the first storage device, and the second token is generated based on an identifier and an LBA of the second storage device.

24 . The storage system of claim 21 , wherein the third storage device receives the first data packet and the second data packet through a compute express link (CXL) switch.

25 . The storage system of claim 21 , wherein the third storage device is configured to receive a command from a host, and perform the integrity verification based on the command.

26 . The storage system of claim 25 , wherein the third storage device is configured to receive a plurality of third tokens, and determine whether the plurality of third tokens comprise tokens that match the first token and the second token.

27 . The storage system of claim 26 , wherein the third storage device determines that the integrity verification is successful if the plurality of third tokens include tokens that match the first token and the second token, and determines that the integrity verification fails if the plurality of third tokens do not include tokens that match the first token and the second token.

28 . The storage system of claim 27 , wherein when the integrity verification fails, the third storage device re-requests an error data packet corresponding to a token for which the integrity verification fails.

29 . The storage system of claim 28 , wherein the third storage device re-requests the error data packet by sending a request to the host or to a storage device among the first storage device and the second storage device corresponding to the error data packet.

30 . The storage system of claim 21 , wherein the third storage device is configured to:
obtain a first reference tag and a first application tag based on the first data packet and the second data packet, determine whether the first reference tag and the first application tag match a pre-stored second reference tag and a pre-stored second application tag, and store the recovered data chunk when the first reference tag and the first application tag match the second reference tag and the second application tag.

31 . The storage system of claim 30 , wherein the third storage device is configured to obtain the first reference tag and the first application tag by performing an XOR operation on the first token and the second token.

32 . A recovery method performed by a storage system comprising a plurality of storage devices forming a redundant array of inexpensive disks (RAID), comprising:
outputting, by a first storage device of the plurality of storage devices, a first data packet including a first token corresponding to the first storage device and a first data chunk, outputting, by a second storage device of the plurality of storage devices, a second data packet including a second token corresponding to the second storage device and a second data chunk, and receiving, by a third storage device of the plurality of storage devices, the first data packet and the second data packet, performing integrity verification using the first token and the second token, and generating a recovered data chunk that corresponds to a data chunk having an error using the first data chunk and the second data chunk.

33 . The recovery method of claim 32 , further comprising:
receiving, by the third storage device, a plurality of third tokens from a host, wherein performing integrity verification comprises:
determining whether the plurality of third tokens include tokens that match the first token and the second token.

34 . The recovery method of claim 33 , wherein determining whether the plurality of third tokens include tokens that match the first token and the second token comprises:
determining that the integrity verification is successful when the plurality of third tokens include tokens that match the first token and the second token, and determining that the integrity verification fails when the plurality of third tokens do not include tokens that match the first token and the second token.

35 . The recovery method of claim 34 , further comprising:
re-requesting, when the integrity verification fails, an error data packet corresponding to a token for which the integrity verification fails.

36 . A storage system, comprising:
a first storage device, and a plurality of second storage devices configured to form a redundant array of inexpensive disks (RAID) set with the first storage device and communicate with each other through a first interface, wherein the plurality of second storage devices are configured to receive a plurality of first tokens corresponding to each of the plurality of second storage devices and a first command from a host, generate a plurality of data packets including the plurality of first tokens and data chunks in response to the first command, and output the plurality of data packets through the first interface, and wherein the first storage device is configured to receive a second command and a plurality of second tokens from the host, perform integrity verification by comparing the plurality of first tokens and the plurality of second tokens in response to the second command, and generate a recovered data chunk that corresponds to a data chunk having an error using the data chunks if the integrity verification is successful.

37 . The storage system of claim 36 , wherein the first storage device is configured to determine the integrity verification is successful when the plurality of first tokens match the plurality of second tokens, and determine the integrity verification fails when the plurality of first tokens do not match the plurality of second tokens.

38 . The storage system of claim 36 , wherein the first interface comprises a compute express link (CXL) switch.

39 . The storage system of claim 36 ,
wherein one of the data chunks is a parity data chunk, and wherein the parity data chunk is generated by performing an exclusive OR (XOR) operation on other data chunks other than the parity data chunk among the data chunks and a data chunk of the first storage device.

40 . The storage system of claim 36 , wherein the first storage device is configured to generate the recovered data chunk by performing an XOR operation on the data chunks.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Lee Jongwon

Classifications

• G06F3/0659 Primary

  Command handling arrangements, e.g. command buffers, queues, command scheduling · CPC title

• G06F3/0689

  Disk arrays, e.g. RAID, JBOD · CPC title

• G06F13/4221

  being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus · CPC title

• G06F13/4022

  using switching circuits, e.g. switching matrix, connection or expansion network (G06F13/4009 takes precedence) · CPC title

• G06F13/1668

  Details of memory controller · CPC title