Tsv-enabled hybrid silicon photonics-on-glass package

Patent metadata

Field	Value
Publication number	US-2025341686-A1
Application number	US-202418653708-A
Country	US
Kind code	A1
Filing date	May 2, 2024
Priority date	May 2, 2024
Publication date	Nov 6, 2025
Grant date	—

Abstract

An electro-optical device is disclosed. The device includes a glass substrate having a plurality of through-glass vias. The device also includes a photonic integrated circuit hybrid bonded to the glass substrate by way of a metal-to-metal, oxide-to-oxide hybrid bond. The PIC has a plurality of through-silicon vias that are coupled with the through-glass vias. The device also includes an electronic integrated circuit coupled with the photonic integrated circuit. A method of assembling a device, or a plurality of devices, is also disclosed.

First claim

We claim:

1 . A device, comprising:
a glass substrate having a plurality of through-glass vias (TGVs); a photonic integrated circuit (PIC) hybrid bonded to the glass substrate by way of a metal-to-metal, oxide-to-oxide hybrid bond, the PIC having a plurality of through-silicon vias (TSVs) that are coupled with the TGVs; and an electronic integrated circuit (EIC) coupled with the PIC.

2 . The device of claim 1 , wherein an edge of the PIC that provides an optical coupling interface is coplanar with a side edge of the glass substrate.

3 . The device of claim 1 , wherein a thickness of the PIC is 120 microns or less.

4 . The device of claim 1 , wherein the EIC is coupled with the PIC by way of a metal-to-metal, oxide-to-oxide hybrid bond, a thermocompression bond, a copper pillar flip chip process, or a microbump flip chip process.

5 . The device of claim 4 , wherein the PIC has a substrate-interface surface and a stackable-interface surface defining a thickness of the PIC, and wherein the PIC has a metal via connected to a metal pad at the stackable-interface surface.

6 . The device of claim 5 , wherein a contact surface of the metal pad is flush with the stackable-interface surface of the PIC.

7 . The device of claim 1 , further comprising:
a second chip hybrid bonded or flip chipped attached to the glass substrate.

8 . The device of claim 1 , wherein the PIC and the EIC form an optical engine that is one of a plurality of optical engines coupled with the glass substrate, and wherein one or more integrated circuits are coupled with the glass substrate and with the plurality of optical engines.

9 . The device of claim 1 , further comprising:
a fiber coupled with the glass substrate, wherein the glass substrate defines a platform pocket in which the PIC is arranged, and wherein the glass substrate has a waveguide arranged to match with the fiber coupled with the glass substrate, the waveguide couples the fiber with a spot size convertor of the PIC.

10 . The device of claim 9 , wherein the glass substrate defines a pocket in which the fiber is arranged, and wherein the fiber is passively optically coupled with the waveguide.

11 . The device of claim 9 , wherein the fiber is actively optically coupled with the waveguide at a diced facet of the glass substrate by way of a fiber array unit.

12 . The device of claim 1 , further comprising:
a fiber coupled with the glass substrate, wherein the glass substrate includes a multiplexing device embedded therein, and wherein the multiplexing device is coupled with the fiber by way of a waveguide of the glass substrate.

13 . The device of claim 1 , further comprising:
a fiber coupled with the glass substrate, wherein the glass substrate has a first side edge and a second side edge defining a length of the glass substrate, and wherein the glass substrate has a first section and a second section, the first section extends from the first side edge to an optical edge defining, at least in part, a platform pocket in which the PIC is arranged, and the second section extends between the optical edge and the second side edge, and wherein the TGVs are arranged in the first section and a waveguide embedded within the glass substrate extends from the optical edge to the fiber.

14 . The device of claim 13 , wherein the second section is thicker than the first section.

15 . The device of claim 1 , wherein the PIC has a substrate-interface surface and a stackable-interface surface defining a thickness of the PIC, and wherein at least one TSV of the plurality of TSVs extends through a silicon handle of the PIC and is flush with the substrate-interface surface.

16 . A method, comprising:
hybrid bonding a plurality of photonic integrated circuits (PICs) to a glass substrate wafer, the plurality of PICs each having through-silicon vias (TSVs) and the glass substrate wafer having a plurality of through-glass vias (TGVs) coupled with the TSVs of the plurality of PICs when the PICs are hybrid bonded to the glass substrate wafer; attaching a plurality of electronic integrated circuits (EICs) to respective ones of the plurality of PICs; attaching a plurality of light sources to respective ones of the plurality of PICs; and performing wafer singulation to create respective electro-optical packages, with each electro-optical package including a glass substrate separated from the glass substrate wafer, at least one of the plurality of PICs, at least one of the plurality of EICs, and at least one of the plurality of light sources, wherein, in performing the wafer singulation, at least one electro-optical package of the electro-optical packages is diced through the glass substrate and a PIC of the at least one electro-optical package to create an optical interface of the PIC that is coplanar with a diced edge of the glass substrate.

17 . The method of claim 16 , wherein in performing the wafer singulation, at least two electro-optical packages of the electro-optical packages are diced through the glass substrates and the PICs of the at least two electro-optical packages concurrently.

18 . The method of claim 16 , further comprising:
performing, prior to wafer singulation, a wafer level test using a test card to test which ones of the electro-optical packages satisfy an operational threshold.

19 . The method of claim 16 , further comprising:
coupling a fiber array unit to the optical interface of the PIC.

20 . An apparatus, comprising:
a glass substrate having a plurality of through-glass vias (TGVs); an integrated circuit (IC) connected to the glass substrate; and at least one device coupled with the IC, the device comprising:
a photonic integrated circuit (PIC) hybrid bonded to the glass substrate and having a plurality of through-silicon vias (TSVs) coupled with the TGVs; and
an EIC coupled with the PIC.

Assignees

• Cisco Tech Inc

Inventors

• Tummidi Ravi S
• Thacker Hiren D
• Schlepple Norbert

Classifications

• G02B6/305

  and having an integrated mode-size expanding section, e.g. tapered waveguide · CPC title

• G02B6/4243 Primary

  Mounting of the optical light guide into a groove (mounting optical light guides into a groove in general G02B6/3636) · CPC title

• G02B6/4274

  Electrical aspects (G02B6/4263 and G02B6/4265 take precedence) · CPC title

• G02B6/4259 Primary

  of the transparent type · CPC title

• G02B6/4204

  the coupling comprising intermediate optical elements, e.g. lenses, holograms (encapsulated active devices H01S5/02208) · CPC title