Bandwidth extension for a voltage buffer

Patent metadata

Field	Value
Publication number	US-2025330131-A1
Application number	US-202418643131-A
Country	US
Kind code	A1
Filing date	Apr 23, 2024
Priority date	Apr 23, 2024
Publication date	Oct 23, 2025
Grant date	—

Abstract

In certain aspects, a voltage buffer includes a first source follower having an input and an output, and a second source follower having an input and an output. The voltage buffer also includes a first transistor, wherein a drain of the first transistor is coupled to the output of the first source follower, and a first coupling capacitor coupled between a gate of the first transistor and the input of the second source follower. The voltage buffer also includes a second transistor, wherein a drain of the second transistor is coupled to the output of the second source follower, and a second coupling capacitor coupled between a gate of the second transistor and the input of the first source follower. The voltage buffer further includes a current source coupled to a source of the first transistor and a source of the second transistor.

First claim

What is claimed is:

1 . A voltage buffer, comprising:
a first transistor, wherein a gate of the first transistor is coupled to a first input of the voltage buffer, and a source of the first transistor is coupled to a first output of the voltage buffer; a first current source coupled to the source of the first transistor; a second transistor, wherein a gate of the second transistor is coupled to a second input of the voltage buffer, and a source of the second transistor is coupled to a second output of the voltage buffer; a second current source coupled to the source of the second transistor; a third transistor, wherein a drain of the third transistor is coupled to the source of the first transistor; a first coupling capacitor coupled between a gate of the third transistor and the second input of the voltage buffer; a fourth transistor, wherein a drain of the fourth transistor is coupled to the source of the second transistor; a second coupling capacitor coupled between a gate of the fourth transistor and the first input of the voltage buffer; and a third current source coupled to a source of the third transistor and a source of the fourth transistor.

2 . The voltage buffer of claim 1 , wherein:
a drain of the first transistor and a drain of the second transistor are coupled to a supply rail; the first current source is coupled between the source of the first transistor and a ground; the second current source is coupled between the source of the second transistor and the ground; the third current source is coupled between the source of the third transistor and the ground; and the third current source is coupled between the source of the fourth transistor and the ground.

3 . The voltage buffer of claim 2 , wherein each of the first transistor, the second transistor, the third transistor, and the fourth transistor comprises a respective n-type field effect transistor (NFET).

4 . The voltage buffer of claim 1 , wherein:
a drain of the first transistor and a drain of the second transistor are coupled to a ground; the first current source is coupled between the source of the first transistor and a supply rail; the second current source is coupled between the source of the second transistor and the supply rail; the third current source is coupled between the source of the third transistor and the supply rail; and the third current source is coupled between the source of the fourth transistor and the supply rail.

5 . The voltage buffer of claim 4 , wherein each of the first transistor, the second transistor, the third transistor, and the fourth transistor comprises a respective p-type field effect transistor (PFET).

6 . The voltage buffer of claim 1 , wherein the third current source comprises a programmable current source.

7 . The voltage buffer of claim 6 , wherein each of the first current source and the second current source comprises a respective programmable current source.

8 . The voltage buffer of claim 1 , wherein the first output of the voltage buffer is coupled to a first input of an analog-to-digital converter (ADC), and the second output of the voltage buffer is coupled to a second input of the ADC.

9 . The voltage buffer of claim 1 , wherein the first current source comprises a fifth transistor, the second current source comprises a sixth transistor, the third current source comprises a seventh transistor, and the voltage buffer further comprises a bias circuit configured to bias a gate of the fifth transistor, a gate of the sixth transistor, and a gate of the seventh transistor.

10 . The voltage buffer of claim 9 , wherein the bias circuit comprises:
a reference current source; and an eighth transistor, wherein a drain of the eighth transistor is coupled to the reference current source, and a gate of the eighth transistor is coupled to the drain of the eighth transistor, the gate of the fifth transistor, the gate of the sixth transistor, and the gate of the seventh transistor.

11 . A voltage buffer, comprising:
a first source follower having an input and an output; a second source follower having an input and an output; a first transistor, wherein a drain of the first transistor is coupled to the output of the first source follower; a first coupling capacitor coupled between a gate of the first transistor and the input of the second source follower; a second transistor, wherein a drain of the second transistor is coupled to the output of the second source follower; a second coupling capacitor coupled between a gate of the second transistor and the input of the first source follower; and a current source coupled to a source of the first transistor and a source of the second transistor.

12 . The voltage buffer of claim 11 , wherein the current source comprises a programmable current source.

13 . The voltage buffer of claim 11 , wherein the output of the first source follower is coupled to a first input of an analog-to-digital converter (ADC), and the output of the second source follower is coupled to a second input of the ADC.

14 . The voltage buffer of claim 11 , wherein the current source comprises a third transistor, and the voltage buffer further comprises a bias circuit configured to bias the third transistor.

15 . The voltage buffer of claim 14 , wherein the bias circuit comprises:
a reference current source; and a fourth transistor, wherein a drain of the fourth transistor is coupled to the reference current source, and a gate of the fourth transistor is coupled to the drain of the fourth transistor and the gate of the third transistor.

16 . A method for operating a voltage buffer, wherein the voltage buffer includes a first source follower and a second source follower, the method comprising:
receiving a first input voltage and a second input voltage; steering a current of a current source to the first source follower during a first time period in which the second input voltage is greater than the first input voltage; and steering the current of the current source to the second source follower during a second time period in which the first input voltage is greater than the second input voltage.

17 . The method of claim 16 , further comprising:
driving an input of the first source follower with the first input voltage; and driving an input of the second source follower with the second input voltage.

Assignees

• Qualcomm Inc

Inventors

• Tang Yongjian
• Arcudia Kenneth Luis

Classifications

• H03F2203/45644

  the LC comprising a cross coupling circuit, e.g. comprising two cross-coupled transistors · CPC title

• H03F2203/5003

  the sources of two source followers are differentially coupled · CPC title

• H03F2203/5033

  Two source followers are controlled at their inputs by a differential signal · CPC title

• H03F3/45179

  using MOSFET transistors as the active amplifying circuit (H03F3/45278 takes precedence) · CPC title

• H03F1/42 Primary

  Modifications of amplifiers to extend the bandwidth · CPC title