Variable resistance memory device including protrusions and recesses

Patent metadata

Field	Value
Publication number	US-2025329353-A1
Application number	US-202519038977-A
Country	US
Kind code	A1
Filing date	Jan 28, 2025
Priority date	Apr 17, 2024
Publication date	Oct 23, 2025
Grant date	—

Abstract

A variable resistance memory device includes: a substrate; a plurality of wiring contacts arranged on the substrate; an isolation insulating layer disposed on the plurality of wiring contacts; and a plurality of variable resistance pattern structures arranged on the isolation insulating layer, wherein the plurality of variable resistance pattern structures constitute a plurality of memory cells, and are spaced apart from one another in a horizontal direction, wherein the isolation insulating layer includes a protrusion that is defined by an isolation recess, and wherein four adjacent variable resistance pattern structures among the plurality of variable resistance pattern structures are respectively arranged at four vertices of a square, and the protrusion is arranged in a central region of the square.

First claim

What is claimed is:

1 . A variable resistance memory device comprising:
a substrate; a plurality of wiring contacts arranged on the substrate; an isolation insulating layer disposed on the plurality of wiring contacts; and a plurality of variable resistance pattern structures arranged on the isolation insulating layer, wherein the plurality of variable resistance pattern structures constitute a plurality of memory cells, and are spaced apart from one another in a horizontal direction, wherein the isolation insulating layer comprises a protrusion that is defined by an isolation recess, and wherein four adjacent variable resistance pattern structures among the plurality of variable resistance pattern structures are respectively arranged at four vertices of a square, and the protrusion is arranged in a central region of the square.

2 . The variable resistance memory device of claim 1 , wherein a bottom surface of the isolation recess is at a vertical level that is lower than a top surface of the protrusion and higher than a bottom surface of the isolation insulating layer.

3 . The variable resistance memory device of claim 2 , wherein a horizontal width of the isolation recess in a diagonal direction of the square is less than a horizontal width of the isolation recess in a direction in which a side of four sides of the square extend.

4 . The variable resistance memory device of claim 2 , wherein an uppermost end of the isolation insulating layer and bottom surfaces of the plurality of variable resistance pattern structures are at a substantially same vertical level as each other, and are at a higher vertical level than the top surface of the protrusion.

5 . The variable resistance memory device of claim 4 , further comprising a plurality of lower electrode contacts connected to the plurality of wiring contacts, wherein the isolation insulating layer covers side surfaces of the plurality of lower electrode contacts, and
wherein the bottom surfaces of the plurality of variable resistance pattern structures contact top surfaces of the plurality of lower electrode contacts and top surfaces of portions of the isolation insulating layer that covers side surfaces of the plurality of lower electrode contacts.

6 . The variable resistance memory device of claim 1 , wherein the protrusion is not arranged on four sides of the square.

7 . The variable resistance memory device of claim 1 , wherein a first surface of the isolation insulating layer in the isolation recess extends from a bottom surface of the isolation recess toward the variable resistance pattern structure with a first angle with respect to the substrate, and a second surface of the isolation insulating layer extends from a bottom surface of the isolation recess toward the protrusion with a second angle, which is greater than the first angle, with respect to the substrate.

8 . The variable resistance memory device of claim 1 , wherein the isolation insulating layer comprises a first isolation insulating layer and a second isolation insulating layer covering the first isolation insulating layer, and
wherein the isolation recess passes through the second isolation insulating layer, but does not pass through the first isolation insulating layer.

9 . The variable resistance memory device of claim 8 , wherein the second isolation insulating layer comprises an insulating material with a dielectric constant that is lower than that of the first isolation insulating layer.

10 . The variable resistance memory device of claim 8 , wherein a maximum thickness of the second isolation insulating layer is greater than a maximum thickness of the first isolation insulating layer.

11 . A variable resistance memory device comprising:
a substrate; a plurality of lower electrode contacts arranged on the substrate; an isolation insulating layer covering sidewalls of the plurality of lower electrode contacts; and a plurality of variable resistance pattern structures spaced apart from one another in a horizontal direction on the isolation insulating layer to form a plurality of memory cells, and connected to the plurality of lower electrode contacts, wherein the isolation insulating layer comprises a protrusion that is defined by an isolation recess, wherein, among the plurality of variable resistance pattern structures, a first variable resistance pattern structure is spaced apart from a second variable resistance pattern structure by a first distance and is spaced apart from a third variable resistance pattern structure by a second distance that is greater than the first distance in a direction that is different than a direction in which the first distance extends, and wherein the protrusion is not arranged between the first variable resistance pattern structure and the second variable resistance pattern structure, and is arranged between the first variable resistance pattern structure and the third variable resistance pattern structure.

12 . The variable resistance memory device of claim 11 , wherein the plurality of variable resistance pattern structures are arranged in a row in a first horizontal direction and are arranged in zigzags in a second horizontal direction that is orthogonal to the first horizontal direction, wherein the first variable resistance pattern structure and the second variable resistance pattern structure are arranged in a diagonal direction with respect to each of the first horizontal direction and the second horizontal direction, and
wherein the first variable resistance pattern structure and the third variable resistance pattern structure are arranged in the first horizontal direction or the second horizontal direction.

13 . The variable resistance memory device of claim 11 , wherein the plurality of variable resistance pattern structures are arranged in a row and in zigzags in a first horizontal direction and a second horizontal direction that is orthogonal to the first horizontal direction, wherein the first variable resistance pattern structure and the second variable resistance pattern structure are arranged in the first horizontal direction or the second horizontal direction, and
wherein the first variable resistance pattern structure and the third variable resistance pattern structure are arranged in a diagonal direction with respect to each of the first horizontal direction and the second horizontal direction.

14 . The variable resistance memory device of claim 11 , wherein a bottom surface of the isolation recess is at a vertical level that is lower than a top surface of the protrusion and higher than a bottom surface of the isolation insulating layer, and
wherein a horizontal width of the isolation recess in a direction that extends between the first variable resistance pattern structure and the second variable resistance pattern structure is greater than a horizontal width of the isolation recess in a direction that extends between the first variable resistance pattern structure and the third variable resistance pattern structure.

15 . The variable resistance memory device of claim 11 , wherein an uppermost end of the isolation insulating layer, top surfaces of the plurality of lower electrode contacts, and bottom surfaces of the plurality of variable resistance pattern structures are at a substantially same vertical level as each other and are at a vertical level that is higher than a top surface of the protrusion.

16 . The variable resistance memory device of claim 15 , wherein the bottom surfaces of the plurality of variable resistance pattern structures are disposed on top surfaces of the plu

Assignees

• Samsung Electronics Co Ltd

Inventors

• Lee Kilho
• Kim Yongjae
• Kim Junhoe
• Ryu Kyounghun
• Park Junho
• Bae Byoungjae
• Son Myoungsu
• Jeon Jihyeon
• Jo Hyeonah

Classifications

• H10N50/01

  Manufacture or treatment · CPC title

• H10B61/00

  Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices · CPC title

• H10B63/80

  Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays · CPC title

• G11C5/063 Primary

  Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay · CPC title

• G11C11/1675

  Writing or programming circuits or methods · CPC title