Delay compensation in conductive trace structures

Patent metadata

Field	Value
Publication number	US-2025324509-A1
Application number	US-202519251250-A
Country	US
Kind code	A1
Filing date	Jun 26, 2025
Priority date	Jun 26, 2025
Publication date	Oct 16, 2025
Grant date	—

Abstract

An apparatus, including: a simulator configured to estimate signal propagation delays for a plurality of conductive trace structures, wherein the conductive trace structures include at least one tabbed routing structure; a compensator configured to determine trace-specific delay compensation values based on measured actual signal propagation delays obtained from PCB test coupons that include the tabbed routing structure and calculate compensated physical trace lengths using the trace-specific delay compensation values to achieve signal timing alignment; and a correlator configured to correlate estimated signal propagation delays with the measured actual signal propagation delays.

First claim

1 . An apparatus, comprising:
a simulator configured to estimate signal propagation delays for a plurality of conductive trace structures, wherein the conductive trace structures include at least one tabbed routing structure; a compensator configured to determine trace-specific delay compensation values based on measured actual signal propagation delays obtained from printed circuit board (PCB) test coupons that include the tabbed routing structure and calculate compensated physical trace lengths using the trace-specific delay compensation values to achieve signal timing alignment; and a correlator configured to correlate estimated signal propagation delays with the measured actual signal propagation delays.

2 . The apparatus of claim 1 , wherein the tabbed routing structure comprises variable geometry based on impedance requirements.

3 . The apparatus of claim 1 , wherein the conductive trace structures comprise mixed routing segments including non-tabbed microstrip segments and tabbed microstrip segments.

4 . The apparatus of claim 3 , wherein the compensator is further configured to calculate composite delay values for the mixed routing segments by determining weighted average delays based on segment lengths and respective propagation delays.

5 . The apparatus of claim 1 , wherein the trace-specific delay compensation values replace fixed delay compensation factors.

6 . The apparatus of claim 1 , wherein the conductive trace structures comprise stripline trace structures and microstrip trace structures.

7 . The apparatus of claim 6 , wherein the stripline trace structures route clock signals and the microstrip trace structures route command and control signals.

8 . The apparatus of claim 1 , wherein the simulator is configured to estimate the signal propagation delays using transmission line models that account for material properties and trace geometry.

9 . The apparatus of claim 1 , wherein the compensator is further configured to input the trace-specific delay compensation values into layout constraint tools to calculate the compensated physical trace lengths.

10 . The apparatus of claim 1 , wherein the PCB test coupons are positioned at board edges or near unused pin areas.

11 . A system, comprising:
a plurality of conductive trace structures including at least one tabbed routing structure; one or more printed circuit board (PCB) test coupons formed on the PCB including the tabbed routing structure; and a processor operatively coupled to the PCB and configured to:
estimate signal propagation delays for the conductive trace structures;
determine trace-specific delay compensation values based on measured actual signal propagation delays obtained from the PCB test coupons;
calculate compensated physical trace lengths using the trace-specific delay compensation values to achieve signal timing alignment; and
correlate estimated signal propagation delays with the measured actual signal propagation delays.

12 . The system of claim 11 , wherein the tabbed routing structure comprises variable geometry based on impedance requirements.

13 . The system of claim 11 , wherein the conductive trace structures comprise mixed routing segments including non-tabbed microstrip segments and tabbed microstrip segments.

14 . The system of claim 13 , wherein the processor is further configured to calculate composite delay values for the mixed routing segments by determining weighted average delays based on segment lengths and respective propagation delays.

15 . The system of claim 11 , wherein the trace-specific delay compensation values replace fixed delay compensation factors.

16 . The system of claim 11 , wherein the conductive trace structures comprise stripline trace structures and microstrip trace structures.

17 . The system of claim 16 , wherein the stripline trace structures route clock signals and the microstrip trace structures route command and control signals.

18 . The system of claim 11 , wherein the processor is configured to estimate the signal propagation delays using transmission line models that account for material properties and trace geometry.

19 . The system of claim 11 , wherein the processor is further configured to input the trace-specific delay compensation values into layout constraint tools to calculate the compensated physical trace lengths.

20 . The system of claim 11 , wherein the PCB test coupons are positioned at board edges or near unused pin areas.

Assignees

• Intel Corp

Inventors

• Hung Chi-Yang
• Hsieh Yu-Heng
• Hsu Wei-Che
• Lee Chang-Ming
• Wang Kai-Yang

Classifications

• H01P9/00

  Delay lines of the waveguide type · CPC title

• H01P3/088

  Stacked transmission lines · CPC title

• H05K2201/09236

  Parallel layout · CPC title

• H05K1/0248

  Skew reduction or using delay lines · CPC title

• G06F2119/12

  Timing analysis or timing optimisation · CPC title