I/o request performance improvement using backend as a service

US2025317488A1 · US · A1

Patent metadata
FieldValue
Publication numberUS-2025317488-A1
Application numberUS-202418627649-A
CountryUS
Kind codeA1
Filing dateApr 5, 2024
Priority dateApr 5, 2024
Publication dateOct 9, 2025
Grant date

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

Methods and apparatuses are provided for utilizing additional and available system resources to cache one or more incoming I/O write requests. A storage processor may implement a policy including a Backend as a Service (BEaaS) to use a node pair backend, a fabric network, and other resources to absorb incoming bursts of I/O write requests from a host and direct the requests temporarily to NVMe storage devices. The policy may further use local and/or remote storage arrays connected over the fabric to alleviate strain on local processing resources. The policy may provide for using cut-through writes, including for example, dual-cast operations over PCIe connections, to send I/O requests directly to the NVMe storage devices.

First claim

Opening claim text (preview).

What is claimed is: 1 . A method for use in a storage processor, the method comprising: receiving an input/output (I/O) request; determining a memory utilization threshold; determining a local memory utilization level; and if the local memory utilization level equals or exceeds the memory utilization threshold, using a backend service to transmit the I/O request over a fabric network to a second memory. 2 . The method of claim 1 wherein the backend service executes a remote direct memory access (DMA) operation to transmit the I/O request. 3 . The method of claim 2 wherein the remote DMA operation is executed by a remote processor. 4 . The method of claim 1 wherein the second memory is a RAID-1 array. 5 . The method of claim 1 wherein the I/O request is stored a controller memory buffer (CMB) of the second memory. 6 . The method of claim 1 wherein the local memory utilization level includes a write pending level. 7 . The method of claim 1 further comprising determining the local memory utilization level has decreased below the memory utilization threshold and relocating the I/O request from the second memory to a local cache memory. 8 . The method of claim 1 wherein the memory utilization threshold is determined by a number of memory devices. 9 . The method of claim 1 wherein the fabric network includes an InfiniBand network. 10 . The method of claim 1 wherein the second memory is a non-volatile memory express (NVMe). 11 . A data storage system comprising: a memory; and at least one processor that is operatively coupled to the memory, the at least one processor being configured to perform the operations of: receiving an input/output (I/O) request; determining a memory utilization threshold; determining a local memory utilization level; and if the local memory utilization level equals or exceeds the memory utilization threshold, using a backend service to transmit the I/O request over a fabric network to a second memory. 12 . The data storage system of claim 11 wherein the backend service executes a remote direct memory access (DMA) operation to transmit the I/O request. 13 . The data storage system of claim 12 wherein the remote DMA operation is executed by a remote processor. 14 . The data storage system of claim 11 wherein the second memory is a RAID-1 array. 15 . The data storage system of claim 11 wherein the I/O request is stored a controller memory buffer (CMB) of the second memory. 16 . The data storage system of claim 11 wherein the local memory utilization level includes a write pending level. 17 . The data storage system of claim 11 further comprising determining the local memory utilization level has decreased below the memory utilization threshold and relocating the I/O request from the second memory to a local cache memory. 18 . The data storage system of claim 11 wherein the memory utilization threshold is determined by a number of memory devices. 19 . The data storage system of claim 11 wherein the fabric network includes an InfiniBand network. 20 . A non-transitory computer-readable medium storing one or more processor-executable instructions, which when executed by at least one processor cause the at least one processor to perform the operations of: receiving an input/output (I/O) request; determining a memory utilization threshold; determining a local memory utilization level; and if the local memory utilization level equals or exceeds the memory utilization threshold, using a backend service to transmit the I/O request over a fabric network to a second memory.

Assignees

Inventors

Classifications

  • Distributed or networked storage systems, e.g. storage area networks [SAN], network attached storage [NAS] · CPC title

  • Command handling arrangements, e.g. command buffers, queues, command scheduling · CPC title

  • Data buffering arrangements · CPC title

  • Disk arrays, e.g. RAID, JBOD · CPC title

  • Improving I/O performance · CPC title

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What does patent US2025317488A1 cover?
Methods and apparatuses are provided for utilizing additional and available system resources to cache one or more incoming I/O write requests. A storage processor may implement a policy including a Backend as a Service (BEaaS) to use a node pair backend, a fabric network, and other resources to absorb incoming bursts of I/O write requests from a host and direct the requests temporarily to NVMe …
Who is the assignee on this patent?
Dell Products Lp
What technology area does this patent fall under?
Primary CPC classification H04L67/1097. Mapped technology areas include Electricity.
When was this patent published?
Publication date Thu Oct 09 2025 00:00:00 GMT+0000 (Coordinated Universal Time) (A1). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 10 related publications on this page (citations in our corpus or others sharing the same primary CPC).