Dynamic clock tree planning using feedtiming cost

Patent metadata

Field	Value
Publication number	US-2025315589-A1
Application number	US-202519241219-A
Country	US
Kind code	A1
Filing date	Jun 17, 2025
Priority date	Jun 11, 2021
Publication date	Oct 9, 2025
Grant date	—

Abstract

A processing device identifies a first clock tree topology for a circuit design, the first clock tree topology having a threshold feedthrough count and a first timing solution. The processing device further identifies one or more additional clock tree topologies for the circuit design, each of the one or more additional clock tree topologies having a different respective feedthrough count that is less than the threshold feedthrough count, and each of the one or more additional clock tree topologies comprising a respective timing solution. In addition, the processing device receives a selection of at least one of the first clock tree topology or the one or more additional clock tree topologies, and generates the circuit design according to the selection.

First claim

What is claimed is:

1 . A method comprising:
identifying, by a processing device, a plurality of candidate clock tree topologies for a circuit design, each of the plurality of candidate clock tree topologies having a different respective feed-timing cost parameter; receiving a selection of at least one of the plurality of candidate clock tree topologies based on the different respective feed-timing cost parameters; and generating the circuit design according to the selection.

2 . The method of claim 1 , wherein the plurality of candidate clock tree topologies each comprise a respective clock path extending from a clock source to a load.

3 . The method of claim 2 , wherein the different respective feed-timing cost parameters are based, at least in part, on different respective feedthrough counts of each of the plurality of candidate clock tree topologies.

4 . The method of claim 3 , wherein the circuit design comprises one or more circuit components arranged in a physical layout, and wherein the different respective feedthrough counts each comprise a respective number of times that the respective clock path crosses a boundary of the one or more circuit components.

5 . The method of claim 4 , wherein generating the circuit design according to the selection comprises forming the clock path with respect to the one or more circuit components to have the respective feedthrough count of the selected candidate clock tree topology.

6 . The method of claim 1 , wherein identifying the plurality of clock tree topologies comprises:
performing a number of iterations of a clock tree topology process incorporating the different respective feed-timing cost parameters, each iteration to identify a respective additional clock tree topology; setting an allowed feedthrough count to zero for a first iteration of the number of iterations; and incrementing the allowed feedthrough count by a set amount for any additional iterations of the number of iterations.

7 . The method of claim 4 , wherein each respective feed-timing cost parameter comprises a vector of path-length and encountered feedthroughs count.

8 . A system comprising:
a memory; and a processing device, coupled to the memory and configured to perform operations comprising:
identifying, by a processing device, a plurality of candidate clock tree topologies for a circuit design, each of the plurality of candidate clock tree topologies having a different respective feed-timing cost parameter;
receiving a selection of at least one of the plurality of candidate clock tree topologies based on the different respective feed-timing cost parameters; and
generating the circuit design according to the selection.

9 . The system of claim 8 , wherein the plurality of candidate clock tree topologies each comprise a respective clock path extending from a clock source to a load.

10 . The system of claim 9 , wherein the different respective feed-timing cost parameters are based, at least in part, on different respective feedthrough counts of each of the plurality of candidate clock tree topologies.

11 . The system of claim 10 , wherein the circuit design comprises one or more circuit components arranged in a physical layout, and wherein the different respective feedthrough counts each comprise a respective number of times that the respective clock path crosses a boundary of the one or more circuit components.

12 . The system of claim 11 , wherein generating the circuit design according to the selection comprises forming the clock path with respect to the one or more circuit components to have the respective feedthrough count of the selected candidate clock tree topology.

13 . The system of claim 8 , wherein identifying the plurality of clock tree topologies comprises:
performing a number of iterations of a clock tree topology process incorporating the different respective feed-timing cost parameters, each iteration to identify a respective additional clock tree topology; setting an allowed feedthrough count to zero for a first iteration of the number of iterations; and incrementing the allowed feedthrough count by a set amount for any additional iterations of the number of iterations.

14 . The system of claim 11 , wherein each feed-timing cost parameter comprises a vector of path-length and encountered feedthroughs count.

15 . A non-transitory computer-readable storage medium storing instructions which, when executed, cause a processing device to perform operations comprising:
identifying, by the processing device, a plurality of candidate clock tree topologies for a circuit design, each of the plurality of candidate clock tree topologies having a different respective feed-timing cost parameter; receiving a selection of at least one of the plurality of candidate clock tree topologies based on the different respective feed-timing cost parameters; and generating the circuit design according to the selection.

16 . The non-transitory computer-readable storage medium of claim 15 , wherein the plurality of candidate clock tree topologies each comprise a respective clock path extending from a clock source to a load.

17 . The non-transitory computer-readable storage medium of claim 16 , wherein the different respective feed-timing cost parameters are based, at least in part, on different respective feedthrough counts of each of the plurality of candidate clock tree topologies, and wherein each respective feed-timing cost parameter comprise a vector of path-length and encountered feedthroughs count.

18 . The non-transitory computer-readable storage medium of claim 17 , wherein the circuit design comprises one or more circuit components arranged in a physical layout, and wherein the different respective feedthrough counts each comprise a respective number of times that the respective clock path crosses a boundary of the one or more circuit components.

19 . The non-transitory computer-readable storage medium of claim 18 , wherein generating the circuit design according to the selection comprises forming the clock path with respect to the one or more circuit components to have the respective feedthrough count of the selected candidate clock tree topology.

20 . The non-transitory computer-readable storage medium of claim 15 , wherein identifying the plurality of clock tree topologies comprises:
performing a number of iterations of a clock tree topology process incorporating the respective feed-timing cost parameters, each iteration to identify a respective additional clock tree topology; setting an allowed feedthrough count to zero for a first iteration of the number of iterations; and incrementing the allowed feedthrough count by a set amount for any additional iterations of the number of iterations.

Assignees

• Synopsys Inc

Inventors

• Kumar Vivek
• Gupta Prashant

Classifications

• G06F30/394

  Routing (G06F30/396 takes precedence) · CPC title

• G06F2119/12

  Timing analysis or timing optimisation · CPC title

• G06F30/3312

  Timing analysis · CPC title

• G06F30/392

  Floor-planning or layout, e.g. partitioning or placement · CPC title

• G06F30/398

  Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] (optical proximity correction [OPC] design processes G03F1/36) · CPC title