Battery runtime optimization

Patent metadata

Field	Value
Publication number	US-2025315097-A1
Application number	US-202418628156-A
Country	US
Kind code	A1
Filing date	Apr 5, 2024
Priority date	Apr 5, 2024
Publication date	Oct 9, 2025
Grant date	—

Abstract

An information handling system includes a battery, a central processing unit, and a processor. The central processing unit includes a plurality of processor cores. The processor monitors a relative state of charge of the battery. The processor transmits a first portable code to modify a user-selectable thermal table mode based on the relative state of charge of the battery. The processor transmits a second portable code to disable one of the processor cores of the central processing unit based on the relative state of charge of the battery.

First claim

What is claimed is:

1 . A method comprising:
monitoring, by a processor of an information handling system, a relative state of charge of a battery of the information handling system; modifying a user-selectable thermal table mode based on the relative state of charge of the battery; and transmitting, by the processor, a portable code to disable a processor core in a central processing unit of the information handling system based on the relative state of charge of the battery.

2 . The method of claim 1 , further comprising notifying an operating system of the information handling system to park the processor core.

3 . The method of claim 1 , further comprising determining a processor core type to be disabled.

4 . The method of claim 1 , further comprising determining a number of processor cores to be disabled.

5 . The method of claim 1 , further comprising notifying an operating system that the processor core is offline.

6 . The method of claim 1 , further comprising in response to detecting a system reboot of the information handling system, enabling the processor core.

7 . The method of claim 1 , further comprising in response to detecting a system reboot, resetting a scheduler processor map.

8 . An information handling system, comprising:
a battery; a central processing unit including a plurality of processor cores; and a processor to communicate with the battery, the processor to:
monitor a relative state of charge of the battery;
transmit a first portable code to modify a user-selectable thermal table mode based on the relative state of charge of the battery; and
transmit a second portable code to disable one of the processor cores of the central processing unit based on the relative state of charge of the battery.

9 . The information handling system of claim 8 , wherein the processor is configured to notify an operating system of the information handling system to park the one of the processor cores.

10 . The information handling system of claim 8 , wherein the processor is further configured to determine a processor core type to be disabled.

11 . The information handling system of claim 8 , wherein the processor is further configured to determine a number of the processor cores to be disabled.

12 . The information handling system of claim 8 , wherein the processor is further configured to notify an operating system that the one of the processor cores is offline.

13 . The information handling system of claim 8 , wherein the processor is further configured to enable the one of the processor cores in response to a detection of a system reboot of the information handling system.

14 . The information handling system of claim 8 , wherein the processor is further configured to reset a scheduler processor map in response to a detection of a system reboot.

15 . A non-transitory computer-readable medium to store instructions that are executable to perform operations comprising:
monitoring a relative state of charge of a battery of an information handling system; modifying a user-selectable thermal table mode based on the relative state of charge of the battery; and transmitting a portable code to disable a processor core of the information handling system based on the relative state of charge of the battery.

16 . The non-transitory computer-readable medium of claim 15 , wherein the operations further comprise notifying an operating system of the information handling system to park the processor core.

17 . The non-transitory computer-readable medium of claim 15 , wherein the operations further comprise determining a processor core type to be disabled.

18 . The non-transitory computer-readable medium of claim 15 , wherein the operations further comprise notifying an operating system that the processor core is offline.

19 . The non-transitory computer-readable medium of claim 15 , wherein the operations further comprise in response to detecting a system reboot of the information handling system, enabling the processor core.

20 . The non-transitory computer-readable medium of claim 15 , wherein the operations further comprise in response to detecting a system reboot, resetting a scheduler processor map.

Assignees

• Dell Products Lp

Inventors

• Varma Suraj M
• Khosrowpour Farzad
• North Travis

Classifications

• G06F1/324

  by lowering clock frequency · CPC title

• G06F1/329

  by task scheduling · CPC title

• G06F1/3206

  Monitoring of events, devices or parameters that trigger a change in power modality · CPC title

• G06F1/3234

  Power saving characterised by the action undertaken · CPC title

• G06F1/3243

  Power saving in microcontroller unit · CPC title