Integrated circuit that mitigates supply voltage deviation using compute unit group identifiers

Patent metadata

Field	Value
Publication number	US-2025315093-A1
Application number	US-202519241006-A
Country	US
Kind code	A1
Filing date	Jun 17, 2025
Priority date	Sep 9, 2022
Publication date	Oct 9, 2025
Grant date	—

Abstract

An integrated circuit (IC) includes an array of reconfigurable compute units organized into mutually exclusive groups. Each group includes no more than a reconfigurable number of reconfigurable compute units. Each compute unit includes group identifier circuitry and control circuitry configured to prevent the compute unit from starting to process data until a signal associated with a reconfigurable group identifier of the reconfigurable compute unit is received from the group identifier circuitry, where the reconfigurable group identifier identifies which group of the mutually exclusive groups the compute unit belongs to. According to operation of the group identifier circuitry and the control circuitry, no more than the reconfigurable number of the reconfigurable compute units are allowed to start processing data concurrently to mitigate supply voltage deviation caused by a time rate of change of current drawn by the IC through inductive loads of the IC.

First claim

1 . An integrated circuit (IC), comprising:
an array of reconfigurable compute units organized into mutually exclusive groups, each group including no more than a reconfigurable number of reconfigurable compute units, wherein each reconfigurable compute unit comprises: group identifier circuitry; and control circuitry configured to prevent the compute unit from starting to process data until a signal associated with a reconfigurable group identifier of the reconfigurable compute unit is received from the group identifier circuitry, wherein:
the reconfigurable group identifier identifies which group of the mutually exclusive groups the compute unit belongs to; and
according to operation of the group identifier circuitry and the control circuitry, no more than the reconfigurable number of the reconfigurable compute units are allowed to start processing data concurrently to mitigate supply voltage deviation caused by a time rate of change of current drawn by the IC through inductive loads of the IC.

2 . The IC of claim 1 , wherein the group identifier circuitry comprises:
a register reconfigurable with the group identifier that identifies which group of the mutually exclusive groups the compute unit belongs to; a first counter that increments each clock cycle and resets to zero when reaching a reconfigurable delay value; and a second counter that increments each time the first counter reaches the reconfigurable delay value; wherein the signal is associated with the reconfigurable group identifier of the reconfigurable compute unit when the second counter value matches the group identifier.

3 . The IC of claim 1 , wherein the reconfigurable compute units are statically reconfigurable.

4 . The IC of claim 1 , wherein the supply voltage deviation includes supply voltage overshoot caused by a negative time rate of change of current drawn by the IC.

5 . The IC of claim 1 , wherein the group identifier circuitry includes a counter reconfigurable to synchronously increment with counters of all other compute units such that all counters have the same value each clock cycle.

6 . The IC of claim 1 , wherein:
the control circuitry comprises a state machine having inactive, wait, and run states; the state machine transitions from the inactive state to the wait state in response to an indication that all data dependencies of the compute unit are satisfied; the state machine transitions from the wait state to the run state in response to the signal from the group identifier circuitry; and the control circuitry prevents the compute unit from starting to process data until the state machine enters the run state.

7 . The IC of claim 6 , wherein each compute unit further comprises:
an inactivity counter that increments each clock cycle in which the compute unit is not processing data; wherein the state machine transitions from the run state to the inactive state in response to the inactivity counter reaching a reconfigurable maximum value.

8 . The IC of claim 7 , wherein:
the inactivity counter is reset by a transition from the wait state to the run state; and the inactivity counter is reset by the compute unit processing data.

9 . A method, comprising:
in an integrated circuit (IC) comprising an array of reconfigurable compute units organized into mutually exclusive groups, each group including no more than a reconfigurable number of reconfigurable compute units: preventing, by control circuitry of each reconfigurable compute unit, the compute unit from starting to process data until a signal associated with a reconfigurable group identifier of the reconfigurable compute unit is received from group identifier circuitry of the compute unit, wherein the reconfigurable group identifier identifies which group of the mutually exclusive groups the compute unit belongs to; wherein according to operation of the group identifier circuitry and the control circuitry, no more than the reconfigurable number of the reconfigurable compute units are allowed to start processing data concurrently to mitigate supply voltage deviation caused by a time rate of change of current drawn by the IC through inductive loads of the IC.

10 . The method of claim 9 , further comprising:
reconfiguring a register of the group identifier circuitry with the group identifier that identifies which group of the mutually exclusive groups the compute unit belongs to; incrementing a first counter of the group identifier circuitry each clock cycle and resetting the first counter to zero when reaching a reconfigurable delay value; incrementing a second counter of the group identifier circuitry each time the first counter reaches the reconfigurable delay value; and providing the signal when the second counter value matches the group identifier.

11 . The method of claim 9 , wherein the reconfigurable compute units are statically reconfigurable.

12 . The method of claim 9 , wherein the group identifier circuitry includes a counter reconfigurable to synchronously increment with counters of all other compute units such that all counters have the same value each clock cycle.

13 . The method of claim 9 , wherein the control circuitry comprises a state machine having inactive, wait, and run states, the method further comprising:
transitioning the state machine from the inactive state to the wait state in response to an indication that all data dependencies of the compute unit are satisfied; transitioning the state machine from the wait state to the run state in response to the signal from the group identifier circuitry; and preventing, by the control circuitry, the compute unit from starting to process data until the state machine enters the run state.

14 . The method of claim 13 , further comprising:
incrementing an inactivity counter each clock cycle in which the compute unit is not processing data; and transitioning the state machine from the run state to the inactive state in response to the inactivity counter reaching a reconfigurable maximum value.

15 . A non-transitory computer-readable storage medium having computer program instructions stored thereon that are capable of causing or configuring an integrated circuit (IC), comprising:
an array of reconfigurable compute units organized into mutually exclusive groups, each group including no more than a reconfigurable number of reconfigurable compute units; wherein each reconfigurable compute unit comprises:
group identifier circuitry; and
control circuitry configured to prevent the compute unit from starting to process data until a signal associated with a reconfigurable group identifier of the reconfigurable compute unit is received from the group identifier circuitry,
wherein the reconfigurable group identifier identifies which group of the mutually exclusive groups the compute unit belongs to;
wherein according to operation of the group identifier circuitry and the control circuitry, no more than the reconfigurable number of the reconfigurable compute units are allowed to start processing data concurrently to mitigate supply voltage deviation caused by a time rate of change of current drawn by the IC through inductive loads of the IC.

16 . The non-transitory computer-readable storage medium of claim 15 , wherein the computer program instructions further cause or configure the IC to:
reconfigure a register of the group identifier circuitry with the group identifier that identifies which group of the mutually exclusive groups the compute unit belongs to; increment a first counter of the group identifier circuitry each clock cycle and reset t

Assignees

• Sambanova Systems Inc

Inventors

• Gandhi Darshan
• Shah Manish K
• Prabhakar Raghu
• Grohoski Gregory Frederick
• Choi Youngmoon
• Shin Jinuk

Classifications

• G06F1/08

  Clock generators with changeable or programmable clock frequency · CPC title

• H03K19/17784

  for supply voltage · CPC title

• G06F1/28

  Supervision thereof, e.g. detecting power-supply failure by out of limits supervision · CPC title

• G06F1/3287

  by switching off individual functional units in the computer system · CPC title

• G06F1/3296

  by lowering the supply or operating voltage · CPC title