Transistor and display device including the same

Patent metadata

Field	Value
Publication number	US-2025311562-A1
Application number	US-202519065274-A
Country	US
Kind code	A1
Filing date	Feb 27, 2025
Priority date	Mar 27, 2024
Publication date	Oct 2, 2025
Grant date	—

Abstract

Disclosed is a transistor including an active layer disposed on a substrate, the active layer including an oxide semiconductor material having a first metal, a gate insulating film disposed on the active layer, a gate electrode at least partially overlapping the active layer on the gate insulating film, a first source-drain electrode and a second source-drain electrode respectively connected to a first source-drain region and a second source-drain region of the active layer, while being insulated from the gate electrode, and a second metal oxide insulating film doped with the first metal, the second metal oxide insulating film being disposed between the gate insulating film and the active layer.

First claim

1 . A transistor comprising:
an active layer on a substrate, the active layer including an oxide semiconductor material having a first metal; a gate insulating film on the active layer; a gate electrode at least partially overlapping the active layer on the gate insulating film; a first source-drain electrode and a second source-drain electrode respectively coupled to a first source-drain region and a second source-drain region of the active layer, while being insulated from the gate electrode; and a second metal oxide insulating film doped with the first metal, the second metal oxide insulating film being disposed between the gate insulating film and the active layer.

2 . The transistor according to claim 1 , wherein the second metal oxide insulating film doped with the first metal is an additional gate insulating film.

3 . The transistor according to claim 2 , wherein the additional gate insulating film comprises Ga, Ga—O bonding, a second metal, a second metal-O bonding, and a Ga-second metal bonding, and
wherein the second metal is a metal different from Ga.

4 . The transistor according to claim 1 , wherein the second metal oxide insulating film doped with the first metal includes a first metal, a first metal-O bonding, a second metal, a second metal-O bonding, and a first metal-second metal bonding.

5 . The transistor according to claim 4 , wherein a density of the first metal in the second metal oxide insulating film doped with the first metal increases with a decreasing distance from the active layer.

6 . The transistor according to claim 4 , wherein the density of the second metal or the density of the second metal-O bonding in the second metal oxide insulating film doped with the first metal increases with a decreasing distance from the gate insulating film.

7 . The transistor according to claim 4 , wherein the density of the first metal-O bonding in the second metal oxide insulating film doped with the first metal increases with a decreasing distance from the active layer.

8 . The transistor according to claim 1 , wherein the second metal oxide insulating film doped with the first metal is in contact with a lower surface of the gate insulating film and is in contact with an upper surface of the active layer.

9 . The transistor according to claim 1 , wherein the oxide semiconductor material comprises at least one of an IGZO (InGaZnO)-based oxide semiconductor material, an IGO (InGaO)-based oxide semiconductor material, an IGZTO (InGaZnSnO)-based oxide semiconductor material, a GZTO (GaZnSnO)-based oxide semiconductor material, a GZO (GaZnO)-based oxide semiconductor material, or a GO (GaO)-based oxide semiconductor material.

10 . The transistor according to claim 1 , wherein the first metal comprises Ga.

11 . The transistor according to claim 1 , wherein the second metal comprises one of group 3 (Sc, Y), group 4 (Ti, Zr, Hf), and group 5 (V, Nb, Ta).

12 . The transistor according to claim 1 , wherein the second metal oxide insulating film doped with the first metal is disposed in a pattern corresponding to an area where the gate electrode and the active layer overlap.

13 . The transistor according to claim 1 , wherein the second metal oxide insulating film doped with the first metal is disposed in an area where a channel area of the active layer overlaps, and the gate insulating film is disposed in an area where the entire area of the active layer overlaps.

14 . The transistor according to claim 1 , wherein the second metal oxide insulating film doped with the first metal comprises:
a first additional gate insulating film on the active layer; a second additional gate insulating film on the first additional gate insulating film; and a third additional gate insulating film on the second additional gate insulating film, wherein the first additional gate insulating film is in contact with an upper surface of the active layer, and the third additional gate insulating film is in contact with a lower surface of the gate insulating film.

15 . A display device comprising:
a substrate; a transistor on the substrate; a planarization film on the transistor; a light emitting element on the planarization film; and an encapsulation layer on the light emitting element, wherein the transistor comprises:
an active layer on a substrate, the active layer including an oxide semiconductor material having a first metal;
a gate insulating film on the active layer;
a gate electrode at least partially overlapping the active layer on the gate insulating film;
a first source-drain electrode and a second source-drain electrode respectively coupled to a first source-drain region and a second source-drain region of the active layer, while being insulated from the gate electrode; and
a second metal oxide insulating film doped with the first metal, the second metal oxide insulating film being disposed between the gate insulating film and the active layer.

16 . The display device according to claim 15 , wherein the transistor is a driving transistor.

17 . The display device according to claim 15 , wherein the second metal oxide insulating film doped with the first metal is an additional gate insulating film.

18 . The display device according to claim 17 , wherein the additional gate insulating film comprises Ga, Ga—O bonding, a second metal, a second metal-O bonding, and a Ga-second metal bonding, and
wherein the second metal is a metal different from Ga.

19 . The display device according to claim 15 , wherein the second metal oxide insulating film doped with the first metal includes a first metal, a first metal-O bonding, a second metal, a second metal-O bonding, and a first metal-second metal bonding.

20 . The display device according to claim 15 , wherein the second metal oxide insulating film doped with the first metal is in contact with a lower surface of the gate insulating film and is in contact with an upper surface of the active layer.

Assignees

• Lg Display Co Ltd

Inventors

• Kim Dae Hwan
• Kim Ki Tae
• Kang Min Gu
• Im Seo Yeon
• Kwak Do Hun

Classifications

• H10K59/121

  characterised by the geometry or disposition of pixel elements · CPC title

• H10D30/60

  Insulated-gate field-effect transistors [IGFET] (H10D30/40 takes precedence) · CPC title

• H10D64/512

  Disposition of the gate electrodes, e.g. buried gates · CPC title

• H10D64/514 Primary

  characterised by the insulating layers · CPC title

• H10D30/6723

  having light shields · CPC title