Semiconductor memory device and method of manufacturing the semiconductor memory device

Patent metadata

Field	Value
Publication number	US-2025311191-A1
Application number	US-202519234542-A
Country	US
Kind code	A1
Filing date	Jun 11, 2025
Priority date	Oct 26, 2021
Publication date	Oct 2, 2025
Grant date	—

Abstract

The present technology includes a semiconductor memory device and a method of manufacturing the semiconductor memory device. The semiconductor memory device includes a first stack structure over a lower structure in which a cell region and a slimming region are defined, including a plurality of first gate lines, a first interlayer insulating structure over the first stack structure, a second stack structure over the first interlayer insulating structure, and a plurality of vertical plugs passing through the first stack structure, the first interlayer insulating structure and the second stack structure in the cell region.

First claim

What is claimed is:

1 . A method of manufacturing a semiconductor memory device, the method comprising:
forming a first stack structure on a lower structure in which a cell region and a slimming region are defined; forming a first interlayer insulating structure over the first stack structure; forming a second interlayer insulating structure over the first interlayer insulating structure; forming a second stack structure on the second interlayer insulating structure; forming a vertical plug passing through the second stack structure, the second interlayer insulating structure, the first interlayer insulating structure and the first stack structure in the cell region; and performing an etching process so that an edge of the second stack structure, the second interlayer insulating structure, the first stack structure, and the first interlayer insulating structure has a step shape, a height and a distance of the step shape of the first interlayer insulating structure is different from a height and a distance of the step shape of a portion except for the first interlayer insulating structure, and a height and a distance of the step shape of the second interlayer insulating structure is different from a height and a distance of the step shape of a portion except for the second interlayer insulating structure, in the slimming region.

2 . The method of claim 1 , wherein in the first stack structure, interlayer insulating layers and sacrificial layers are alternately stacked on the lower structure, and then the first interlayer insulating structure is formed, and the first interlayer insulating structure is formed of the same material as the interlayer insulating layers.

3 . The method of claim 1 , wherein the second interlayer insulating structure is formed of the same material as the first interlayer insulating structure.

4 . The method of claim 1 , wherein the etching process is performed by sequentially using mask patterns having an opening exposing the second stack structure and the first stack structure formed in the slimming region and decreasing to a constant length.

5 . The method of claim 4 , wherein etching process is performed so that the second stack structure or the first stack structure exposed by the opening is removed to the same depth each time the mask patterns are changed.

6 . The method of claim 5 , wherein an interlayer insulating layer and a sacrificial layer formed in each of the first stack structure or the second stack structure are removed to substantially the same depth, during the etching process.

7 . The method of claim 6 , wherein the first interlayer insulating structure or the second interlayer insulating structure is removed to a depth substantially equal to the depth to which the interlayer insulating layer and the sacrificial layer are removed from the first stack structure or the second stack structure, during the etching process.

8 . The method of claim 1 ,
wherein forming the vertical plug comprises: forming a vertical hole passing through the second stack structure and the first stack structure; and sequentially forming a memory layer, a channel layer, and a vertical insulating layer along an inner wall of the vertical hole, wherein after sequentially forming the memory layer, the channel layer, and the vertical insulating layer: forming a trench separating the memory layer, the channel layer, and the vertical insulating layer in a vertical direction; and forming an insulating layer inside the trench.

9 . A method of manufacturing a semiconductor memory device, the method comprising:
forming a first stack structure on a lower structure in which a cell region and a slimming region are defined; forming a first interlayer insulating structure on the first stack structure; forming a first vertical plug passing through the first stack structure and the first interlayer insulating structure in the cell region; forming a second interlayer insulating structure on the first interlayer insulating structure; forming a third vertical plug passing through the second interlayer insulating structure in the cell region; forming a third interlayer insulating structure on the second interlayer insulating structure; forming a second stack structure on the third interlayer insulating structure; forming a second vertical plug passing through the second stack structure and the third interlayer insulating structure in the cell region; and performing an etching process so that an edge of the second stack structure, the first to third interlayer insulating structure, and the first stack structure has a step shape, a height and a distance of a step shape of the first interlayer insulating structure is different from a height and a distance of the step shape of a portion except for the first interlayer insulating structure, and a height and a distance of a step shape of the third interlayer insulating structure is different from a height and a distance of the step shape of a portion except for the third interlayer insulating structure, in the slimming region.

10 . The method of claim 9 , wherein the third interlayer insulating structure is thicker than an interlayer insulating layer.

11 . The method of claim 9 , further comprising after performing the etching process so that the edge has the step shape:
forming a vertical channel separation structure separating the second vertical plug, the third vertical plug, and the first vertical plug in a vertical direction.

Assignees

• Sk Hynix Inc

Inventors

• Choi Won Geun
• Kim Jang Won
• Jang Jung Shik

Classifications

• H10B12/0335

  Making a connection between the transistor and the capacitor, e.g. plug · CPC title

• H10B12/34

  the transistor being at least partially in a trench in the substrate · CPC title

• H10B43/50

  characterised by the boundary region between the core and peripheral circuit regions · CPC title

• H10B43/27 Primary

  the channels comprising vertical portions, e.g. U-shaped channels · CPC title

• H10B12/31 Primary

  having a storage electrode stacked over the transistor · CPC title