Data processing method and data processing apparatus

Patent metadata

Field	Value
Publication number	US-2025310029-A1
Application number	US-202519235465-A
Country	US
Kind code	A1
Filing date	Jun 11, 2025
Priority date	Dec 12, 2022
Publication date	Oct 2, 2025
Grant date	—

Abstract

A data processing method and a data processing apparatus. First, W virtual bits are periodically inserted into a first data stream obtained through first FEC encoding to obtain a second data stream, where each second data stream includes at least one first bit sequence, the first bit sequence includes L=P+W bits, the P bits are from the first data stream, and the W bits are padded virtual bits. Then, second FEC encoding is performed on the second data stream to obtain a third data stream, where a second bit sequence is obtained by performing second FEC encoding on each first bit sequence, and the second bit sequence includes b codewords. Next, W virtual bits in each second bit sequence of the third data stream are deleted to obtain a fourth data stream. Then, processing including modulation is performed on m fourth data streams to obtain Y modulated symbol streams.

First claim

What is claimed is:

1 . A data processing method, comprising:
separately performing first data processing on m first data streams obtained through first forward error correction (FEC) encoding to obtain m second data streams, wherein m is an integer greater than 1, each of the second data streams comprises at least one first bit sequence, the first bit sequence comprises L bits, P bits in the first bit sequence are from the first data stream, W bits in the first bit sequence are padded virtual bits, W is an integer greater than or equal to 1, and L=P+W; separately performing second FEC encoding on the m second data streams to obtain m third data streams, wherein each of the third data streams comprises at least one second bit sequence, each second bit sequence is obtained by performing second FEC encoding on the first bit sequence, the second bit sequence comprises b codewords, b is an integer greater than 1, each of the codewords comprises N bits, N=K+S, K represents a quantity of information bits in the codeword, S represents a quantity of parity bits in the codeword, K is an integer greater than or equal to 1, S is an integer greater than or equal to 1, and L=K×b; separately performing second data processing on the m third data streams to obtain m fourth data streams, wherein each of the fourth data streams comprises at least one third bit sequence, each third bit sequence is obtained by performing second data processing on the second bit sequence, the third bit sequence comprises M remaining bits other than the virtual bits in the second bit sequence, and M=N×b−W; and performing third data processing on the m fourth data streams to obtain Y modulated symbol streams, wherein Y is an integer greater than or equal to 1, the third data processing comprises modulation, and a value of a baud rate of each of the modulated symbol streams is an integer multiple of a value of a reference clock frequency.

2 . The method according to claim 1 , wherein the value of the baud rate of each of the modulated symbol streams is an integer multiple of 156.25M.

3 . The method according to claim 1 , wherein b and W satisfy the following relationship:

4
⁢
2
⁢
5

4

×

b
×
N

-
W

b
×
K

-
W

⁢
G

=

a
×
φ
⁢
M

,

wherein a is an integer greater than or equal to 1, φ represents the value of the reference clock frequency, G represents 10{circumflex over ( )}9, and M represents 10{circumflex over ( )}6.

4 . The method according to claim 1 , wherein N=128 and K=120; and
Hamming (128,120) is used for the second FEC encoding; or the second FEC encoding is performing bitwise exclusive OR on every two consecutive information bits in K=120 information bits to obtain 60 bits, and performing Hamming (68,60) encoding on the 60 bits to obtain S=8 parity bits, wherein a codeword with a length of 128 bits that is obtained through the second FEC encoding comprises the K=120 information bits and the S=8 parity bits.

5 . The method according to claim 4 , wherein W is an integer multiple of 10; and

W
=

40
×
b

2
⁢
3

,

W
=

200
×
b

4
⁢
7

,

W
=

20
×
b

3

,

or
⁢

W

=

440
×
b

4
⁢
9

.

6 . The method according to claim 1 , wherein N=148 and K=140; and
Hamming (148,140) is used for the second FEC encoding; or the second FEC encoding is performing bitwise exclusive OR on every two consecutive information bits in K=140 information bits to obtain 70 bits, and performing Hamming (78,70) encoding on the 70 bits to obtain S=8 parity bits, wherein a codeword with a length of 148 bits that is obtained through the second FEC encoding comprises the K=140 information bits and the S=8 parity bits.

7 . The method according to claim 6 , wherein W=4×b,

W
=

2
⁢
2
⁢
0
×
b

2
⁢
1

,

W
=

1
⁢
8
⁢
0
×
b

11

,

W
=

500
×
b

2
⁢
3

,

or
⁢

W

=

80
×
b

3

Assignees

• Huawei Tech Co Ltd

Inventors

• Huang Kechao
• Yan Zengchao
• Yang Xiaoling
• Huang Qinhui
• Ma Huixiao

Classifications

• H04L1/0047

  Decoding adapted to other signal detection operation (in conjunction with sequence estimation or equalization H04L25/03286) · CPC title

• H04L1/0071

  Use of interleaving (interleaving per se H03M13/27) · CPC title

• H04L1/0061

  Error detection codes · CPC title

• H04L1/0059

  Convolutional codes · CPC title

• H04L1/006

  Trellis-coded modulation · CPC title