Method for manufacturing electronic device and electronic device prepared by using the same

Patent metadata

Field	Value
Publication number	US-2025309102-A1
Application number	US-202519065474-A
Country	US
Kind code	A1
Filing date	Feb 27, 2025
Priority date	Mar 28, 2024
Publication date	Oct 2, 2025
Grant date	—

Abstract

A method for manufacturing an electronic device includes the following steps: providing a substrate; forming a first conductive layer on the substrate; patterning the first conductive layer to form a first conductive pattern; forming a second conductive layer on the first conductive pattern; and patterning the second conductive layer to form a second conductive pattern, wherein the second conductive pattern includes a first sub-pattern and a second sub-pattern, and the first sub-pattern is disposed on the first conductive pattern, wherein a distance between the first conductive pattern and the second sub-pattern is less than a distance between the first sub-pattern and the second sub-pattern.

First claim

1 . A method for manufacturing an electronic device, comprising the following steps:
providing a substrate; forming a first conductive layer on the substrate; patterning the first conductive layer to form a first conductive pattern; forming a second conductive layer on the first conductive pattern; and patterning the second conductive layer to form a second conductive pattern, wherein the second conductive pattern comprises a first sub-pattern and a second sub-pattern, and the first sub-pattern is disposed on the first conductive pattern, wherein a distance between the first conductive pattern and the second sub-pattern is less than a distance between the first sub-pattern and the second sub-pattern.

2 . The method of claim 1 , further comprising the following steps before the step of patterning the second conductive layer:
forming an etching barrier layer on the second conductive layer; and patterning the etching barrier layer to form a mask, wherein the mask and a portion of the second conductive layer are overlapped in a top view direction of the substrate.

3 . The method of claim 2 , wherein the second conductive pattern further comprises a third sub-pattern adjacent to the second sub-pattern after the step of patterning the second conductive layer, wherein the second sub-pattern corresponds to the portion of the second conductive layer.

4 . The method of claim 3 , wherein a distance between the third sub-pattern and the second sub-pattern is less than the distance between the first sub-pattern and the second sub-pattern.

5 . The method of claim 1 , wherein the same etching substance has etching selectivity for the first conductive layer and the second conductive layer.

6 . The method of claim 1 , wherein a material of the first conductive layer comprises indium tin oxide (ITO), molybdenum, molybdenum nitride (MoN), tungsten-molybdenum alloy (MoW), tungsten or a combination thereof.

7 . The method of claim 1 , wherein a material of the second conductive layer comprises titanium nitride (TiN), titanium aluminum alloy (TiAl), titanium aluminum nitride (TiAlN), titanium aluminum oxide (TiAlO), titanium silicon aluminum (TiSiAl), titanium tungsten alloy (TiW), titanium tungsten nitride (TiWN), aluminum nitride (AlNx) or a combination thereof.

8 . The method of claim 1 , further comprising the following steps before the step of patterning the second conductive layer:
forming a photoresist layer on the second conductive layer; and patterning the photoresist layer to form a patterned photoresist, wherein the patterned photoresist and the second conductive pattern are overlapped in the top view direction of the substrate after the step of patterning the second conductive layer.

9 . The method of claim 8 , wherein the patterned photoresist comprises a first sub-photoresist pattern and a second sub-photoresist pattern, wherein in the top view direction of the substrate, the first sub-photoresist pattern and the first sub-pattern are overlapped, and the second sub-photoresist pattern and the second sub-pattern are overlapped.

10 . The method of claim 9 , wherein a distance between the first conductive pattern and the second sub-pattern is less than a distance between the first sub-photoresist pattern and the second sub-photoresist pattern.

11 . The method of claim 1 , wherein the step of patterning the first conductive layer further includes a step of etching the first conductive layer with a first etching substance, and the step of patterning the second conductive layer further includes a step of etching the second conductive layer with a second etching substance, wherein the second etching substance has etching selectivity for the first conductive layer and the second conductive layer.

12 . The method of claim 11 , wherein the first etching substance is different from the second etching substance.

13 . The method of claim 11 , wherein the first etching substance comprises oxalic acid (H 2 C 2 O 4 ), nitric acid (HNO 3 ) or a combination thereof.

14 . The method of claim 11 , wherein the second etching substance comprises sulfur hexafluoride (SF 6 ), carbon tetrafluoride (CF 4 ), boron trichloride (BCl 3 ), chlorine (Cl 2 ) or a combination thereof.

15 . An electronic device, comprising:
a substrate; a first conductive pattern disposed on the substrate; and a second conductive pattern comprising a first sub-pattern and a second sub-pattern, wherein the first sub-pattern is disposed on the first conductive pattern, and the second sub-pattern is disposed on the substrate, wherein a distance between the first conductive pattern and the second sub-pattern is less than a distance between the first sub-pattern and the second sub-pattern.

16 . The electronic device of claim 15 , wherein the second conductive pattern further comprises a third sub-pattern, and a distance between the third sub-pattern and the second sub-pattern is less than the distance between the first sub-pattern and the second sub-pattern.

17 . The electronic device of claim 16 , further comprising a mask disposed on the second sub-pattern.

18 . The electronic device of claim 16 , wherein the third sub-pattern is adjacent to the second sub-pattern.

19 . The electronic device of claim 15 , wherein a material of the first conductive layer comprises indium tin oxide (ITO), molybdenum, molybdenum nitride (MoN), tungsten-molybdenum alloy (MoW), tungsten or a combination thereof.

20 . The electronic device of claim 15 , wherein a material of the second conductive pattern comprises titanium nitride (TiN), titanium aluminum alloy (TiAl), titanium aluminum nitride (TiAlN), titanium aluminum oxide (TiAlO), titanium silicon aluminum (TiSiAl), titanium tungsten alloy (TiW), titanium tungsten nitride (TiWN), aluminum nitride (AlNx) or a combination thereof.

Assignees

• Innolux Corp

Inventors

• Tsai Yu-Ting
• Liao Wei-Ju
• Liu Yu-Tsung
• Yao I-An

Classifications

• H05K2201/0959

  Plated through-holes or plated blind vias filled with insulating material · CPC title

• H05K3/0023

  by exposure and development of a photosensitive insulating layer · CPC title

• H05K3/108

  by semi-additive methods; masks therefor (characterised by metallic etch mask H05K3/062; electroplating methods or apparatus H05K3/241) · CPC title

• H05K3/4644

  by building the multilayer layer by layer, i.e. build-up multilayer circuits (making via holes in the insulating layers H05K3/0011; special circuit boards as base or core whereon the multilayer is built H05K3/4602) · CPC title

• H10W20/4446

  Refractory-metal alloys · CPC title