Multilayer ceramic capacitor

Patent metadata

Field	Value
Publication number	US-2025308799-A1
Application number	US-202519046733-A
Country	US
Kind code	A1
Filing date	Feb 6, 2025
Priority date	Mar 27, 2024
Publication date	Oct 2, 2025
Grant date	—

Abstract

A multilayer ceramic capacitor includes an inner layer portion including inner dielectric layers and internal electrode layers laminated alternately in a lamination direction. Each of the internal electrode layers includes an end portion in a width direction including a region A with a low continuity of each of the internal electrode layers at the end portion. The region A has a line coverage lower than that in a middle portion in the width direction of each of the internal electrode layers.

First claim

What is claimed is:

1 . A multilayer ceramic capacitor comprising:
a multilayer body including an inner layer portion including a plurality of inner dielectric layers and a plurality of internal electrode layers alternately laminated in a lamination direction, outer layer portions sandwiching the inner layer portion in the lamination direction, two main surfaces opposed to each other in the lamination direction, two lateral surfaces opposed to each other in a width direction orthogonal or substantially orthogonal to the lamination direction, and two end surfaces opposed to each other in a length direction orthogonal or substantially orthogonal to the lamination direction and the width direction; and a pair of external electrodes each on a corresponding one of the two end surfaces and each connected to the plurality of internal electrode layers; wherein each of the plurality of internal electrode layers includes an end portion in the width direction including a region A with a low continuity of each of the plurality of internal electrode layers at the end portion; and the region A includes a line coverage lower than that in a middle portion in the width direction of each of the plurality of internal electrode layers.

2 . The multilayer ceramic capacitor according to claim 1 , wherein the region A has a length in the width direction of about 5 μm or more and about 20 μm or less.

3 . The multilayer ceramic capacitor according to claim 1 , wherein the line coverage of the region A is about 50% or less.

4 . The multilayer ceramic capacitor according to claim 1 , wherein the multilayer ceramic capacitor has a dimension in the length direction of about 0.2 mm or more and about 10 mm or less, a dimension in the width direction of about 0.1 mm or more and about 10 mm or less, and a dimension in the lamination direction of about 0.1 mm or more and about 10 mm or less.

5 . The multilayer ceramic capacitor according to claim 1 , wherein the multilayer body has a rectangular or substantially rectangular parallelepiped shape.

6 . The multilayer ceramic capacitor according to claim 1 , wherein each of the plurality of inner dielectric layers includes BaTiO 3 , CaTiO 3 , SrTiO 3 , or CaZrO 3 as a main component.

7 . The multilayer ceramic capacitor according to claim 6 , wherein each of the plurality of inner dielectric layers includes a Mn compound, a Fe compound, a Cr compound, a Co compound, or a Ni compound as a subcomponent.

8 . The multilayer ceramic capacitor according to claim 1 , wherein a thickness of each of the plurality of inner dielectric layers is about 0.2 μm or more and about 15 μm or less.

9 . The multilayer ceramic capacitor according to claim 1 , wherein each of the plurality of internal electrode layers mainly includes Ni.

10 . The multilayer ceramic capacitor according to claim 1 , wherein each of the plurality of internal electrode layers includes Cu, Ag, Pd, Sn or Au, or an alloy including at least one of Cu, Ag, Pd, Sn or Au.

11 . The multilayer ceramic capacitor according to claim 1 , wherein a thickness of each of the plurality of internal electrode layers is about 0.2 μm or more and about 2.0 μm or less.

12 . The multilayer ceramic capacitor according to claim 1 , wherein a thickness of each of the plurality of internal electrode layers is about 0.30 μm or more and about 0.35 μm or less.

13 . The multilayer ceramic capacitor according to claim 1 , wherein each of the pair of external electrodes includes a base electrode layer and a plated layer on the base electrode layer.

14 . The multilayer ceramic capacitor according to claim 13 , wherein the base electrode layer includes metal and glass.

15 . The multilayer ceramic capacitor according to claim 14 , wherein the glass includes at least one of B, Si, Ba, Mg, Al, or Li.

16 . The multilayer ceramic capacitor according to claim 14 , wherein the metal includes Cu as a main component.

17 . The multilayer ceramic capacitor according to claim 14 , wherein the metal includes at least one of Ni, Ag, Pd or Au, and an alloy including at least one of Ni, Ag, Pd or Au.

18 . The multilayer ceramic capacitor according to claim 1 , wherein a thickness of each of the pair of external electrodes is about 2 μm or more and about 220 μm or less.

19 . The multilayer ceramic capacitor according to claim 13 , wherein the plated layer includes a Ni plated layer and a Sn plate layer on the Ni plated layer.

20 . The multilayer ceramic capacitor according to claim 13 , wherein the plated layer includes a Cu plated layer, a Ni plated layer on the Cu plated layer, and a Sn plated layer on the Ni plated layer.

Assignees

• Murata Manufacturing Co

Inventors

• Tanaka Kouta
• Sugita Hiroaki
• Miyauchi Satoshi

Classifications

• H01G4/12

  Ceramic dielectrics {(H01G4/085 takes precedence)} · CPC title

• H01G4/005

  Electrodes · CPC title

• H01G4/30 Primary

  Stacked capacitors (H01G4/33 takes precedence) · CPC title

• Y02E60/13

  Energy storage using capacitors · CPC title

• H01G4/232

  electrically connecting two or more layers of a stacked or rolled capacitor · CPC title