Display panel and display device

Patent metadata

Field	Value
Publication number	US-2025299614-A1
Application number	US-202318861604-A
Country	US
Kind code	A1
Filing date	Jun 30, 2023
Priority date	Oct 25, 2022
Publication date	Sep 25, 2025
Grant date	—

Abstract

A display panel and a display device are provided. The display panel includes a substrate; a shielding layer disposed on the substrate; and a driving circuit layer disposed on a side of the shielding layer away from the substrate. The driving circuit layer includes a driving function transistor in the scan driving circuit sub-area. The shielding layer includes a first shielding portion between the driving function transistor and the substrate, and the first shielding portion is configured to be supplied with a variable voltage.

First claim

1 . A display panel comprising a display area, a non-display area adjacent to the display area, and the non-display area comprising a scan driving circuit sub-area;
the display panel further comprising: a substrate; a shielding layer disposed on the substrate; and a driving circuit layer disposed on a side of the shielding layer which is away from the substrate, wherein the driving circuit layer comprises a driving function transistor disposed in the scan driving circuit sub-area; wherein the shielding layer comprises a first shielding portion between the driving function transistor and the substrate, and the first shielding portion is configured to be supplied with a voltage that is variable.

2 . The display panel according to claim 1 , wherein the driving circuit layer further comprises a display function transistor disposed in the display area, and the shielding layer further comprises a second shielding portion disposed between the display function transistor and the substrate;
wherein when both the driving function transistor and the display function transistor are turned on, a polarity of the voltage of the first shielding portion is opposite to a polarity of a voltage of the second shielding portion, and when both the driving function transistor and the display function transistor are turned off, the polarity of the voltage of the first shielding portion is the same as the polarity of the voltage of the second shielding portion.

3 . The display panel according to claim 1 , wherein a polarity of the voltage of the first shielding portion is a negative polarity when the driving function transistor is turned on, and a polarity of the voltage of the first shielding portion is a positive polarity when the driving function transistor is turned off.

4 . The display panel according to claim 1 , wherein the driving function transistor comprises an active layer, a gate, a source, and a drain, wherein the active layer is provided on a side of the first shielding portion which is away from the substrate, the gate is provided on a side of the active layer which is away from the first shielding portion, the source and the drain are provided on a side of the gate which is away from the active layer, and the source and the drain overlap with two sides of the active layer;
wherein the first shielding portion is electrically connected to the gate.

5 . The display panel according to claim 1 , wherein the display panel further comprises a scan driving circuit disposed in the scan driving circuit sub-area, the scan driving circuit comprises a plurality of scan driving units cascaded, and each of the plurality of scan driving units comprises a first node control module, a second node control module, and an output module;
the first node control module is electrically connected to a first node and electrically connected to the second node control module, and the first node control module is configured to control a potential of the first node; the second node control module is electrically connected to a second node and electrically connected to the first node control module, and the second node control module is configured to control a potential of the second node; the output module is electrically connected to the first node, the second node, and a signal output terminal of a present stage, and the output module is configured to control a potential of the signal output terminal of the present stage under a control of the potential of the first node and the potential of the second node; wherein the driving function transistor is disposed at least in the output module.

6 . The display panel according to claim 5 , wherein the output module comprises a first transistor connected between the signal output terminal of the present stage and the first node, and the driving function transistor comprises the first transistor.

7 . The display panel according to claim 6 , wherein the first node control module is electrically connected to a signal output terminal of a previous stage, the first node control module further comprises a second transistor and a third transistor connected between the signal output terminal of the previous stage and the first transistor, and the driving function transistor further comprises a second transistor and/or a third transistor.

8 . A display panel comprising a display area, a non-display area adjacent to the display area, and the non-display area comprising a scan driving circuit sub-area;
the display panel further comprising: a substrate; a shielding layer disposed on the substrate; and a driving circuit layer disposed on a side of the shielding layer which is away from the substrate, wherein the driving circuit layer comprises one or more driving function transistors disposed in the scan driving circuit sub-area and one or more display function transistors disposed in the display region; wherein the shielding layer comprises one or more first shielding portions each of which is between a corresponding one of the one or more driving function transistors and the substrate, and one or more second shielding portions each of which is disposed between a corresponding one of the one or more display function transistors and the substrate, and the first shielding portion is connected to the second shielding portion.

9 . The display panel according to claim 8 , wherein the one or more driving function transistors comprise a plurality of driving function transistors, and the one or more display function transistors comprise a plurality of display function transistors; the one or more first shielding portions comprise a plurality of first shielding portions each of which is between a corresponding one of the driving function transistors and the substrate, and the one or more second shielding portions comprise a plurality of second shielding portions each of which is between a corresponding one of the display function transistors and the substrate;
wherein the plurality of first shielding portions and the plurality of second shielding portions are connected to form a network structure.

10 . The display panel according to claim 9 , wherein the display panel further comprises a scan driving circuit disposed in the scan driving circuit sub-area, the scan driving circuit comprises a plurality of scan driving units cascaded, and each of the plurality of scan driving units comprises a first node control module, a second node control module, and an output module;
the first node control module is electrically connected to a first node and electrically connected to the second node control module, and the first node control module is configured to control a potential of the first node; the second node control module is electrically connected to a second node, and electrically connected to the first node control module, and the second node control module is configured to control a potential of the second node; the output module is electrically connected to the first node, the second node, and a signal output terminal of a present stage, and the output module is configured to control a potential of the signal output terminal of the present stage under a control of the potential of the first node and the potential of the second node; wherein the one or more driving function transistors are disposed at least in the output module.

11 . The display panel according to claim 10 , wherein the output module comprises a first transistor connected between the signal output terminal of the present stage and the first node, and the driving function transistor comprises the first transistor.

12 . The display panel according to claim 11 , wherein the first node control module is ele

Assignees

• Wuhan China Star Optoelectronics Semiconductor Display Tech Co Ltd

Inventors

• Wang Wei
• Huang Qing

Classifications

• G09G3/3677

  suitable for active matrices only · CPC title

• G09G3/20

  for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix {no fixed position being assigned to or needed to be assigned to the individual characters or partial characters} · CPC title

• G09G2310/08

  Details of timing specific for flat panels, other than clock recovery · CPC title

• G09G2310/0254

  Control of polarity reversal in general, other than for liquid crystal displays · CPC title

• G09G2300/043

  Compensation electrodes or other additional electrodes in matrix displays related to distortions or compensation signals, e.g. for modifying TFT threshold voltage in column driver · CPC title