Memory Chiplet Architecture

Patent metadata

Field	Value
Publication number	US-2025298760-A1
Application number	US-202519086047-A
Country	US
Kind code	A1
Filing date	Mar 20, 2025
Priority date	Mar 22, 2024
Publication date	Sep 25, 2025
Grant date	—

Abstract

A system and a method are disclosed for improving memory chiplets. In an embodiment, a memory chiplet comprises a memory stack and a base die. The base die includes a thru-silicon via (TSV) coupled to the memory stack, a memory controller coupled to the TSV through a first interface, and a die-to-die (D 2 D) interconnect. The base die further includes a link layer coupled to the memory controller configured to map a bus interface from the memory controller to a D 2 D interface of the D 2 D interconnect. Data mapped by the link layer is transmitted to a second chiplet with a parallel link layer corresponding to the link layer.

First claim

What is claimed is:

1 . A memory chiplet comprising:
a memory stack; and a base die comprising: a thru-silicon via (TSV) coupled to the memory stack; a memory controller coupled to the TSV through a first interface; a die-to-die (D2D) interconnect; and a link layer coupled to the memory controller configured to map a bus interface from the memory controller to a D2D interface of the D2D interconnect to be transmitted over a D2D interconnect to a second chiplet with a parallel link layer corresponding to the link layer.

2 . The memory chiplet of claim 1 , further comprising a core logic in the base die.

3 . The memory chiplet of claim 2 , wherein the core logic is one or more of a low power double data rate (LPDDR) logic, a compute logic, an accelerator logic, or an I/O chiplet.

4 . The memory chiplet of claim 1 , further comprising a second memory stack coupled to the TSV.

5 . The memory chiplet of claim 1 , further comprising a second link layer coupled to the memory controller configured to map the bus interface from the memory controller to the D2D interface of the D2D interconnect.

6 . The memory chiplet of claim 5 , further comprising a multiplexer coupled to the memory controller and coupled to both the link layer and the second link layer configured to select between the link layer and the second link layer.

7 . The memory chiplet of claim 6 , wherein the multiplexer is electronically fused around the link layer and the second link layer.

8 . The memory chiplet of claim 5 , wherein the second link layer is configured to map the bus interface from the memory controller to the D2D interface of the D2D interconnect to be transmitted over the D2D interconnect to a third chiplet with a second parallel link layer corresponding to the second link layer.

9 . The memory chiplet of claim 8 , wherein the memory chiplet is configured to switch between using the link layer when communicating with the second chiplet and the second link layer when communicating with the third chiplet.

10 . The memory chiplet of claim 1 , further comprising a second link layer coupled to the TSV configured to map a memory interface from the TSV to a D2D interface of the D2D interconnect to be transmitted over a D2D interconnect to a second compute chiplet with a memory controller and a second parallel link layer corresponding to the second link layer.

11 . The memory chiplet of claim 1 , wherein the memory stack is a high-bandwidth memory (HBM) stack.

12 . The memory chiplet of claim 1 , wherein the TSV is a high-bandwidth memory (HBM) 3D PHY.

13 . A system comprising:
a memory chiplet comprising:
a memory stack;
a thru-silicon via (TSV) coupled to the memory stack; a memory controller coupled to the TSV through a first interface; a first die-to-die (D2D) interconnect; and a first link layer coupled to the memory controller and the D2D interconnect configured to map a bus interface from the memory controller to a D2D interface of the D2D interconnect; a second chiplet comprising:
a second D2D interconnect;
a core logic; and
a second link layer coupled to the second D2D interconnect and the core logic configured to reverse the mapping of the first link layer from the second D2D interconnect to the core logic; and an interposer or substrate configured to couple the memory chiplet to the second chiplet.

14 . The system of claim 13 , wherein the memory chiplet further comprises a second memory stack coupled to the TSV.

15 . The system of claim 13 , further comprising a third link layer coupled to the memory controller configured to map the bus interface from the memory controller to the D2D interface of the D2D interconnect.

16 . The system of claim 15 , further comprising a multiplexer, coupled to the memory controller and coupled to both the first link layer and the third link layer, configured to select between the first link layer and the third link layer.

17 . The system of claim 16 , wherein the multiplexer is electronically fused around the first link layer and the third link layer.

18 . The system of claim 15 , wherein the third link layer is configured to map the bus interface from the memory controller to the D2D interface of the D2D interconnect, the system further comprising:
a third chiplet comprising:
a third D2D interconnect;
a second core logic; and
a fourth link layer coupled to the third D2D interconnect and the second core logic configured to reverse the mapping of the third link layer from the third D2D interconnect to the second core logic.

19 . The system of claim 13 , wherein the memory chiplet further comprises a third link layer coupled to the TSV configured to map a memory interface from the TSV to the D2D interface of the D2D interconnect, the system further comprising:
a third chiplet comprising:
a third D2D interconnect;
a second core logic;
a second memory controller; and
a fourth link layer coupled to the third D2D interconnect and the second memory controller configured to reverse the mapping of the third link layer from the third D2D interconnect to the second memory controller.

20 . A method comprising:
receiving, at a memory controller in a base die of a chiplet, data from a memory stack of the chiplet through a through-silicon-via; receiving, at a link layer of a base die in the chiplet, a signal in memory controller interface format from the memory controller; mapping the signals from the memory controller interface format to a D2D interface format; sending the signal in the D2D interface format to a D2D interconnect of the base die; and transferring the signal from the chiplet to another chiplet through an interposer or substrate.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Yang Li
• Yao Chih-Wei
• Quach Nhon
• Yee Kevin

Classifications

• G06F2213/16

  Memory access · CPC title

• G06F13/1684 Primary

  using multiple buses · CPC title