Non-volatile memory device, a storage device including the non-volatile memory device and a method of operating the storage device

Patent metadata

Field	Value
Publication number	US-2025298517-A1
Application number	US-202519029778-A
Country	US
Kind code	A1
Filing date	Jan 17, 2025
Priority date	Mar 22, 2024
Publication date	Sep 25, 2025
Grant date	—

Abstract

Provided are a non-volatile memory device, a storage device including the non-volatile memory device, and a method of operating the storage device. The non-volatile memory device includes a memory cell array including first and second sub-blocks that are respectively formed from first and second portions of memory cell strings that extend through a plurality of wordlines stacked on a substrate, the first and second sub-blocks each being selectable as a unit of an erase operation; and control logic configured to calculate an off-cell count based on a first voltage for a plurality of memory cells in the first sub-block, calculate an on-cell count based on a second voltage for the plurality of memory cells, and control an operation for the first sub-block to be performed based on an operating condition corresponding to disturb information generated by the off-cell count and the on-cell count.

First claim

What is claimed is:

1 . A non-volatile memory device comprising:
a memory cell array including first and second sub-blocks that are respectively formed from first and second portions of memory cell strings that extend through a plurality of wordlines stacked on a substrate, the first and second sub-blocks each being selectable as a unit of an erase operation; and control logic configured to calculate an off-cell count based on a first voltage for a plurality of memory cells in the first sub-block, calculate an on-cell count based on a second voltage for the plurality of memory cells, and control an operation for the first sub-block to be performed based on an operating condition corresponding to disturb information generated by the off-cell count and the on-cell count.

2 . The non-volatile memory device of claim 1 , wherein:
the first sub-block includes a first wordline included in the plurality of wordlines, the off-cell count is generated by calculating a change value in a memory cell determined to be an on-cell among a plurality of first memory cells connected to the first wordline based on the first voltage, and the on-cell count is generated by calculating a change value of a memory cell determined to be an off-cell among the plurality of first memory cells based on the second voltage.

3 . The non-volatile memory device of claim 1 , wherein:
the control logic is configured to control, in response to receiving a read command, a read operation for the first sub-block to be performed based on an adjusted read voltage corresponding to the disturb information.

4 . The non-volatile memory device of claim 1 ,
wherein the control logic is configured to:
adjust a first set of adjusted read voltages corresponding to the disturb information, and
control a read operation for the first sub-block based on the first set of adjusted read voltages, and
wherein when the disturb information implies a distribution increase in threshold voltages for the plurality of memory cells, each of the first set of adjusted read voltages adjusted by the control logic is respectively higher than a corresponding read voltage of a set of initial read voltages initially set.

5 . The non-volatile memory device of claim 1 , wherein:
the control logic is configured to control, in response to receiving an erase command, an erase operation for the first sub-block to be performed based on an adjusted erase voltage corresponding to the disturb information.

6 . The non-volatile memory device of claim 5 , wherein:
when the disturb information implies a distribution increase in a threshold voltage for the plurality of memory cells, the erase operation for the first sub-block is performed based on the adjusted erase voltage that is higher than an initial erase voltage initially set.

7 . The non-volatile memory device of claim 5 , wherein:
when the disturb information implies a distribution increase in a threshold voltage for the plurality of memory cells, the erase operation for the first sub-block is performed based on an adjusted erase time that is longer than an initial erase time initially set.

8 . The non-volatile memory device of claim 1 , wherein:
the disturb information includes a cell count change value calculated by subtracting the on-cell count from the off-cell count.

9 . The non-volatile memory device of claim 1 , wherein:
the plurality of memory cells are triple level cells (TLCs) configured to be programmed to one of an erased state and first to seventh states that are sequentially higher, the first to the seventh states are divided by first to seventh program verification voltages that have sequentially higher voltage levels, the first voltage is the first program verification voltage, and the second voltage is the seventh program verification voltage.

10 . A storage device comprising:
a non-volatile memory device including a memory cell array including first and second sub-blocks that are respectively formed from first and second portions of memory cell strings that extend through a plurality of wordlines stacked on a substrate, the first and second sub-blocks each being selectable as a unit of an erase operation, and control logic configured to generate disturb information for the first sub-block based on an on-cell count and an off-cell count for a plurality of memory cells in the first sub-block, and adjust an operating condition for the first sub-block based on the disturb information; and a storage controller configured to log a first command for the second sub-block, and provide the non-volatile memory device with a disturb check command for the disturb information based on log information from a logging operation.

11 . The storage device of claim 10 , wherein:
the first and second sub-blocks are connected to a first bitline, and when an erase operation is performed on the second sub-block, the first sub-block is floated.

12 . The storage device of claim 11 , wherein:
the storage controller is configured to provide the disturb check command to the non-volatile memory device based on first program/erase cycle log information for the first command and a predetermined value.

13 . The storage device of claim 12 , wherein:
the memory cell array further includes a third sub-block connected to the first bitline and divided from the first and second sub-blocks by the plurality of wordlines, and the storage controller is further configured to log a second command for the third sub-block, compare the predetermined value with a sum of second program/erase cycle log information for the second command and the first program/erase cycle log information, and provide the disturb check command to the non-volatile memory device.

14 . The storage device of claim 11 , wherein:
the storage controller is configured to provide the disturb check command to the non-volatile memory device based on read log information for the first command and a predetermined value.

15 . The storage device of claim 11 , wherein:
in response to the erase operation being performed for the first sub-block, the log information is cleared.

16 . The storage device of claim 10 ,
wherein the control logic is configured to:
generate the off-cell count by calculating a change value of a memory cell determined to be an on-cell based on a first voltage for the plurality of memory cells,
generate the on-cell count by calculating a change value of a memory cell determined to be an off-cell based on a second voltage for the plurality of memory cells, and
calculate the off-cell count and the on-cell count to generate the disturb information.

17 . A method of operating a storage device, the method comprising:
logging a command of a first sub-block to monitor a disturb circumstance of a second sub-block connected to a first bitline connected to the first sub-block, wherein the first and second sub-blocks are respectively formed from first and second portions of memory cell strings that extend through a plurality of wordlines stacked on a substrate; providing a disturb check command for the second sub-block based on a log operation for the command to a non-volatile memory device including the first and second sub-blocks; generating disturb information by calculating based on an on-cell count and an off-cell count for a memory cell of a first wordline in the second sub-block; storing the disturb information; and performing an operation on the second sub-block based on an operating condition corresponding to the disturb information.

18 . The met

Assignees

• Samsung Electronics Co Ltd

Inventors

• Seo Donghyun
• Yu Jae-Duk
• Park Sang Soo
• Park Jonghoon

Classifications

• G06F3/0679

  Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP] · CPC title

• G06F3/0658

  Controller construction arrangements · CPC title

• G11C16/3459

  Circuits or methods to verify correct programming of nonvolatile memory cells · CPC title

• G11C16/26

  Sensing or reading circuits; Data output circuits · CPC title

• G11C16/14

  Circuits for erasing electrically, e.g. erase voltage switching circuits · CPC title