Semiconductor device

Patent metadata

Field	Value
Publication number	US-2025294721-A1
Application number	US-202418944282-A
Country	US
Kind code	A1
Filing date	Nov 12, 2024
Priority date	Mar 15, 2024
Publication date	Sep 18, 2025
Grant date	—

Abstract

A semiconductor device includes an integrated circuit structure including conductive regions; a capacitor including lower electrode structures connected to the conductive regions and spaced apart on the integrated circuit structure, a dielectric layer covering the lower electrode structures, and an upper electrode structure on the dielectric layer; and supporter structures interconnecting the lower electrode structures, the supporter structures include an upper supporter structure interconnecting upper regions of the lower electrode structures and spaced apart, and a lower supporter structure interconnecting the lower electrode structures and spaced apart, side surfaces of the upper supporter patterns and an side surface of the upper region of the lower electrode structures define an upper open pattern, side surfaces of the lower supporter patterns and a side surface of the lower electrode structure define a lower open pattern, and centers of the upper supporter patterns and centers of the lower supporter patterns are aligned.

First claim

What is claimed is:

1 . A semiconductor device, comprising:
an integrated circuit structure including conductive regions; a capacitor including lower electrode structures electrically connected to the conductive regions of the integrated circuit structure, a dielectric layer covering the lower electrode structures, and an upper electrode structure on the dielectric layer, the lower electrode structures being spaced apart from each other on the integrated circuit structure; and supporter structures interconnecting the lower electrode structures, wherein the supporter structures include,
an upper supporter structure interconnecting upper regions of the lower electrode structures to each other, the upper supporter structure including upper supporter patterns spaced apart from each other, and
a lower supporter structure including lower supporter patterns interconnecting the lower electrode structures to each other, the lower supporter patterns spaced apart from each other below the upper supporter patterns,
wherein external side surfaces of the upper supporter patterns of the upper supporter structure and external side surfaces of the upper regions of the lower electrode structures connected to each other by the upper supporter patterns define an upper open pattern extending in a horizontal direction, wherein external side surfaces of the lower supporter patterns of the lower supporter structure and external side surfaces of the lower electrode structure connected to each other by the lower supporter patterns define a lower open pattern extending in the horizontal direction, and wherein first centers of the upper supporter patterns of the upper supporter structure and second centers of the lower supporter patterns of the lower supporter structure corresponding to the first centers, respectively, are aligned.

2 . The semiconductor device of claim 1 , wherein each of the upper supporter patterns of the upper supporter structure surrounds at least one first lower electrode structure of the lower electrode structures and each of the upper supporter patterns is in contact with at least a portion of a side surface of each of a plurality of second lower electrode structures adjacent to the first lower electrode structure.

3 . The semiconductor device of claim 2 ,
wherein an external side surface of an upper supporter pattern between second lower electrode structures adjacent to each other among the plurality of second lower electrode structures has a convex shape in a direction away from a center of the upper supporter pattern.

4 . The semiconductor device of claim 2 ,
wherein an external side surface of an upper supporter pattern of the upper supporter patterns between second lower electrode structures adjacent to each other among the plurality of second lower electrode structures has a flat surface.

5 . The semiconductor device of claim 2 ,
wherein an external side surface of an upper supporter pattern of the upper supporter patterns between second lower electrode structures adjacent to each other among the plurality of second lower electrode structures has a concave shape in a direction toward a center of the upper supporter pattern.

6 . The semiconductor device of claim 1 , wherein each of the upper supporter patterns of the upper supporter structure surround an entire side surface of a first lower electrode structure of the first lower electrode structures and is in contact with a portion of a side surface of each of a plurality of second lower electrode structures adjacent to the first lower electrode structure.

7 . The semiconductor device of claim 6 , wherein a distance between centers of upper supporter patterns adjacent to each other in the horizontal direction is configured to be 76 nm or more and 100 nm or less.

8 . The semiconductor device of claim 6 , wherein
at least one of the lower supporter patterns of the lower supporter structure surrounds the first lower electrode structure and is in contact with at least a portion of the side surface of each of the plurality of second lower electrode structures adjacent to the first lower electrode structure, and the at least one of the lower supporter patterns is between the upper supporter structure and the integrated circuit structure.

9 . The semiconductor device of claim 8 , wherein a maximum horizontal width of the lower supporter patterns of the lower supporter structure is greater than a maximum horizontal width of the upper supporter patterns of the upper supporter structure.

10 . The semiconductor device of claim 8 , wherein, in a plan view, circumferential surfaces of the second lower electrode structures are in contact with internal side surfaces of the lower supporter patterns.

11 . The semiconductor device of claim 1 , wherein at least one of the upper supporter patterns of the upper supporter structure surrounds entire side surfaces of a plurality of first lower electrode structures of the lower electrode structures, the plurality of first lower electrode structures being most adjacent to each other, and the at least one of the upper supporter patterns is in contact with at least a portion of a side surface of each of a plurality of second lower electrode structures adjacent to the each of the first lower electrode structures.

12 . The semiconductor device of claim 11 , wherein a distance between centers of the upper supporter patterns adjacent to each other in the horizontal direction is configured to be 95 nm or more and 110 nm or less.

13 . The semiconductor device of claim 1 , further comprising:
an intermediate supporter structure between the upper supporter structure and the lower supporter structure, wherein the intermediate supporter structure includes intermediate supporter patterns interconnecting the lower electrode structures to each other and spaced apart from each other, and wherein an external side surface of the intermediate supporter patterns of the intermediate supporter structure and external side surfaces of the lower electrode structures connected to each other by the intermediate supporter patterns define an intermediate open pattern extending in the horizontal direction.

14 . The semiconductor device of claim 13 , wherein third centers of the intermediate supporter patterns of the intermediate supporter structure are aligned with the first centers and the second centers corresponding to the third centers.

15 . The semiconductor device of claim 13 ,
wherein a maximum horizontal width of an intermediate supporter pattern of the intermediate supporter patterns is greater than a maximum horizontal width of an upper supporter pattern of the upper supporter patterns, and wherein a maximum horizontal width of a lower supporter pattern of the lower supporter patterns is greater than a maximum horizontal width of the intermediate supporter pattern.

16 . The semiconductor device of claim 1 , wherein the upper open pattern and the lower open pattern are filled by the upper electrode structure.

17 . A semiconductor device, comprising:
an integrated circuit structure including conductive regions; a capacitor including lower electrode structures electrically connected to the conductive regions of the integrated circuit structure, a dielectric layer covering the lower electrode structures, and an upper electrode structure on the dielectric layer; an upper supporter structure including upper supporter patterns spaced apart from each other, each of the upper supporter patterns surrounds at least one first lower electrode structure of the lower electrode stru

Assignees

• Samsung Electronics Co Ltd

Inventors

• Kim Soyeon
• Kim Suklae

Classifications

• H10D1/692

  Electrodes · CPC title

• H10D1/60

  Capacitors · CPC title

• H10B12/30 Primary

  DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells · CPC title

• H10B12/03

  Making the capacitor or connections thereto · CPC title

• H10B12/315 Primary

  with the capacitor higher than a bit line · CPC title