Memory structure

Patent metadata

Field	Value
Publication number	US-2025294717-A1
Application number	US-202418603264-A
Country	US
Kind code	A1
Filing date	Mar 13, 2024
Priority date	Mar 13, 2024
Publication date	Sep 18, 2025
Grant date	—

Abstract

A memory structure includes a substrate having an upper surface; a first gate structure and a second gate structure disposed on the substrate, separated from each other in a first direction and extend in a second direction, respectively; and a plurality of channel bodies separated from each other in the first direction and a third direction, and penetrating the first gate structure and the second structure, respectively. The first direction, the second direction and the third direction intersect each other. The upper surface is parallel to the first direction and the second direction, and a normal direction of the upper surface is parallel to the third direction. A first length of the first gate structure in the first direction and a second length of the second gate structure in the first direction are different from each other.

First claim

What is claimed is:

1 . A memory structure, comprising:
a substrate, having an upper surface; a first gate structure and a second gate structure, disposed on the substrate, separated from each other in a first direction and extending in a second direction, respectively; and a plurality of channel bodies separated from each other in the first direction and a third direction, and penetrating the first gate structure and the second structure, respectively, wherein the first direction, the second direction and the third direction intersect each other, the upper surface is parallel to the first direction and the second direction, and a normal direction of the upper surface is parallel to the third direction, wherein a first length of the first gate structure in the first direction and a second length of the second gate structure in the first direction are different from each other.

2 . The memory structure according to claim 1 , further comprising:
a plurality of pads, stacked along the third direction and separated from each other along the third direction, each of the pads connecting a first end of a corresponding one of the channel bodies; a first side plug, extending along the third direction and connecting the pads; and a plurality of second side plugs, respectively extending along the third direction and separated from each other in the second direction, each of the second side plugs connecting a second end of a corresponding one of the channel bodies, wherein the second end is opposite to the first end, wherein the first gate structure is closer to the first end than the second gate structure.

3 . The memory structure according to claim 2 , wherein the first length is smaller than the second end.

4 . The memory structure according to claim 2 , wherein the second length is smaller than the first end.

5 . The memory structure according to claim 2 , wherein the first gate structure comprises a plurality of portions, the second gate structures comprises a plurality of portions, the portions of the first gate structure respectively extend along the second direction and are separated from each other along the third direction, the portions of the second gate structure respectively extend along the second direction and are separated from each other along the third direction.

6 . The memory structure according to claim 5 , wherein lengths of the portions of the first gate structure in the second direction are different from each other, and lengths of the portions of the second gate structure in the second direction are different from each other.

7 . The memory structure according to claim 5 , further comprising:
a plurality of first contacts, separated from each other along the second direction and respectively extending along the third direction to electrically contact the a plurality of first landing regions on the portions of the first gate structure, wherein the first landing regions form a staircase structure; and a plurality of second contacts, separated from each other along the second direction and respectively extending along the third direction to electrically contact the a plurality of second landing regions on the portions of the second gate structure, wherein the second landing regions form another staircase structure.

8 . The memory structure according to claim 2 , wherein the first gate structure is a continuous structure in the third direction, and the second gate structure comprises a plurality of portions respectively extending along the second direction and separated from each other along the third direction.

9 . The memory structure according to claim 8 , wherein the first gate structure corresponds to all of the channel bodies, and the portions of the second gate structure respectively correspond to a portion of the channel

10 . The memory structure according to claim 8 , further comprising a plurality of contacts separated from each other along the second direction, and respectively extending along the third direction to electrically contact a plurality of landing regions on the portions of the second gate structure, wherein the landing regions form a staircase structure.

11 . The memory structure according to claim 2 , wherein the first gate structure comprises a plurality of portions respectively extending along the second direction and separated from each other along the third direction, and the second gate structure is a continuous structure in the third direction.

12 . The memory structure according to claim 11 , wherein the portions of the first gate structure respectively correspond to a portion of the channel bodies, and the second gate structure corresponds to all of the channel bodies.

13 . The memory structure according to claim 12 , further comprising a plurality of contacts separated from each other along the second direction, and respectively extending along the third direction to electrically contact a plurality of landing regions on the portions of the first gate structure, wherein the landing regions form a staircase structure.

14 . The memory structure according to claim 1 , further comprising a plurality of dielectric films disposed between the first gate structure and the channel bodies and between the second gate structure and the channel

15 . The memory structure according to claim 2 , wherein the first end comprises a first conductivity type dopant, the second end comprises a second conductivity type dopant, and the second conductivity type dopant is different from the first conductivity type dopant.

16 . The memory structure according to claim 2 , wherein the first side plug serves as a common source line.

17 . The memory structure according to claim 2 , wherein each of the second side plugs serves as a bit line.

18 . The memory structure according to claim 1 , wherein the first gate structure and the second gate structure serve as one or more word lines respectively.

19 . The memory structure according to claim 1 , further comprising a plurality of memory cell units, each of the memory cell units are formed by a corresponding one of the channel bodies, the first gate structure and the second gate structure.

20 . The memory structure according to claim 1 , wherein an operating mechanism of the memory structure is based on a thyristor.

Assignees

• Macronix Int Co Ltd

Inventors

• Chen Wei-Chen
• Lue Hang-Ting

Classifications

• H10B69/00 Primary

  Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices · CPC title

• H10B12/20 Primary

  DRAM devices comprising floating-body transistors, e.g. floating-body cells · CPC title